Trait grand_central_m4::sercom::v2::spi::OpMode [−][src]
pub trait OpMode: Sealed {
const MODE: MODE_A;
const MSSEN: bool;
fn configure(sercom: &RegisterBlock) { ... }
}
Expand description
Type-level enum representing the SPI operating mode
See the documentation on type-level enums for a discussion of the pattern.
The available operating modes are Master
, MasterHWSS
and Slave
.
In Master
mode, the SS
signal must be handled by the user, so SS
must be NoneT
. In MasterHWSS
mode, the hardware drives the SS
line, so SomePad
is required. In Slave
mode, the SS
pad is
required as well, to indicate when data is valid.
Associated Constants
Provided methods
Configure the SPI operating mode
For maximum flexibility, this module chooses to always operate in 32-bit extension mode. The LENGTH counter is used to control the number of byes in each SPI transaction. Due to a hardware bug, ICSPACE must be at least one. See the silicon errata for more details.