Trait grand_central_m4::prelude::_embedded_hal_blocking_spi_Write [−][src]
pub trait _embedded_hal_blocking_spi_Write<W> {
type Error;
fn write(&mut self, words: &[W]) -> Result<(), Self::Error>;
}
Expand description
Blocking write
Associated Types
Required methods
Implementors
Implement Write
for short Spi
transaction Length
s
The Spi
Pads
must be Tx
but NotRx
and the
transaction Length
must be <= 4
. The transfer accepts a
slice of primitive integers, depending on the Length
(u8
,
u16
or u32
).
Because Write
is only implemented when the Pads
are
NotRx
, this implementation never reads the DATA register and
ignores all buffer overflow errors.
Implement Write
for short Spi
transaction Length
s
The Spi
Pads
must be Tx
but NotRx
and the
transaction Length
must be <= 4
. The transfer accepts a
slice of primitive integers, depending on the Length
(u8
,
u16
or u32
).
Because Write
is only implemented when the Pads
are
NotRx
, this implementation never reads the DATA register and
ignores all buffer overflow errors.
Implement Write
for short Spi
transaction Length
s
The Spi
Pads
must be Tx
but NotRx
and the
transaction Length
must be <= 4
. The transfer accepts a
slice of primitive integers, depending on the Length
(u8
,
u16
or u32
).
Because Write
is only implemented when the Pads
are
NotRx
, this implementation never reads the DATA register and
ignores all buffer overflow errors.
Implement Write
for short Spi
transaction Length
s
The Spi
Pads
must be Tx
but NotRx
and the
transaction Length
must be <= 4
. The transfer accepts a
slice of primitive integers, depending on the Length
(u8
,
u16
or u32
).
Because Write
is only implemented when the Pads
are
NotRx
, this implementation never reads the DATA register and
ignores all buffer overflow errors.
Implement Write
for Spi
types with DynLength
The Spi
Pads
must be Tx
. The transfer accepts a slice of u8
with a length equal to the run-time dynamic transaction length. If the slice
length does not match the result of Spi::get_dyn_length
, it will panic.
Because Write
is only implemented when the Pads
are NotRx
, this
implementation never reads the DATA register and ignores all buffer overflow
errors.
impl<P, M, L> Write<u8> for Spi<Config<P, M, L>> where
P: Tx,
M: OpMode,
L: GreaterThan4,
Config<P, M, L>: ValidConfig,
impl<P, M, L> Write<u8> for Spi<Config<P, M, L>> where
P: Tx,
M: OpMode,
L: GreaterThan4,
Config<P, M, L>: ValidConfig,
Implement Write
for longer Spi
transaction Length
s
The Spi
Pads
must be Tx
but NotRx
and the transaction
Length
must be > 4
. The transfer accepts a slice of u8
with a length
equal to the transfer Length
. If the slice length is incorrect, it will
panic.
Because Write
is only implemented when the Pads
are NotRx
, this
implementation never reads the DATA register and ignores all buffer overflow
errors.