pub struct Pipeline {
pub id: usize,
pub scheduler_id: Option<usize>,
pub register_read_cycles: usize,
pub general_purpose: bool,
pub vector: bool,
pub alu: Option<AluCapabilities>,
pub memory_load: bool,
pub memory_store: bool,
pub renaming: bool,
}Expand description
The properties of a CPU pipeline.
This models the complete execution back-end of a CPU, including register file access, an ALU and/or AGU and access to the Load-Store-Unit. As there can be many different things happening in the back-end, a pipeline is highly configurable.
Fields§
§id: usizeIdentification number. Isn’t strictly needed, but helps with error reporting.
scheduler_id: Option<usize>The ID of the scheduler the pipeline uses, if any. Multiple pipelines with the same scheduler ID share a scheduler among them.
register_read_cycles: usizeHow many clock cycles are dedicated to reading register data.
general_purpose: boolIf the pipeline can execute instructions exclusively using the general purpose register file.
vector: boolIf the pipeline can execute instructions using the vector register file.
alu: Option<AluCapabilities>Which types of ALU instructions the pipeline can support, if any.
memory_load: boolIf the pipeline can serve memory read operands.
memory_store: boolIf the pipeline can serve memory write operands.
renaming: boolIf the pipeline makes use of register renaming. If it doesn’t, an instruction can only be issued to this pipeline if every register operand is ready and the output register doesn’t have an instruction already wanting to write to it.