Struct MixedGemm 

pub struct MixedGemm<N>(/* private fields */);

Available on crate feature half only.

The widen-and-FMA mixed-precision GEMM family: Lhs = Rhs = Out = N (a NarrowFloat, either f16 or bf16), with Acc = f32

Trait Implementations

impl<N> Clone for MixedGemm<N>

fn clone(&self) -> Self

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<N> Copy for MixedGemm<N>

impl<N> KernelFamily for MixedGemm<N>

where N: NarrowFloat,

const OUT_IS_ACC: bool = false

Whether a running Acc partial sum can round-trip through C (Out) between kc depth panels without losing precision. This is true exactly when Out == Acc, which is also the default, so a family need not set it unless it narrows on store

type Lhs = N

Left-hand input element type

type Rhs = N

Right-hand input element type

type Acc = f32

Accumulator element type. This is Lhs::Acc in every shipped family. That is f32 or f64 for float, i32 for i8, f32 for f16 or bf16, and the same as Lhs for complex

type Out = N

Output element type

unsafe fn pack_lhs( dst: *mut N, src: *const N, rs: isize, cs: isize, mc: usize, kc: usize, mr: usize, )

Pack an mc x kc LHS block into micropanel-major layout. The result is ceil(mc/mr) panels of mr rows each. Every panel stores one depth step at a time, with mr contiguous rows per step (mr == MR_REG*LANES). A short tail row-block is zero-padded up to mr

unsafe fn pack_rhs( dst: *mut N, src: *const N, rs: isize, cs: isize, kc: usize, nc: usize, nr: usize, )

Pack a kc x nc RHS block into micropanel-major layout. The result is ceil(nc/nr) panels of nr columns each, with every panel stored one depth step at a time and nr contiguous columns per step. A short tail column-block is zero-padded up to nr

unsafe fn microkernel_epi<S, E, const MR_REG: usize, const NR: usize>( simd: S, kc: usize, alpha: f32, beta: f32, alpha_status: AlphaStatus, beta_status: BetaStatus, a: *const N, a_cs: isize, b: *const N, b_rs: isize, b_cs: isize, c: *mut N, rsc: isize, csc: isize, mr_eff: usize, nr_eff: usize, row0: usize, col0: usize, last_k: bool, epi: &E, scratch: *mut f32, )

where S: KernelSimd<N, N, f32, N>, E: Epilogue<Self>,

Compute one MR x NR tile and store the fused Epilogue E applied to each element. row0 and col0 are the tile’s origin in the oriented problem frame, so a per-row or per-column bias can resolve its absolute base. last_k marks the final depth panel, the only one on which an OUT_IS_ACC family may apply the epilogue. Earlier panels store raw Acc partials, per the contract on KernelFamily::OUT_IS_ACC

const FORCE_PACK_LHS: bool = false

Force the driver to always pack the LHS, bypassing its cost-based pack or no-pack decision. Set this when packing is not a plain copy, such as a k-group interleave, a signedness bias, or a conjugation. In that case the driver’s in-place read path would be wrong, not just slower, so the transform must always run. The default is false

const FORCE_PACK_RHS: bool = false

See KernelFamily::FORCE_PACK_LHS

const DEPTH_MULTIPLE: usize = 1

Depth-panel padding multiple. The driver rounds every packed panel’s depth up to this before it sizes and addresses the A/B pack buffers. The default, 1, is a no-op for every homogeneous or widen-and-multiply family

unsafe fn microkernel<S, const MR_REG: usize, const NR: usize>( simd: S, kc: usize, alpha: Self::Acc, beta: Self::Acc, alpha_status: AlphaStatus, beta_status: BetaStatus, a: *const Self::Lhs, a_cs: isize, b: *const Self::Rhs, b_rs: isize, b_cs: isize, c: *mut Self::Out, rsc: isize, csc: isize, mr_eff: usize, nr_eff: usize, scratch: *mut Self::Acc, )

where S: KernelSimd<Self::Lhs, Self::Rhs, Self::Acc, Self::Out>,

Compute one MR x NR output tile and store C <- combine(alpha*A*B, beta*C). MR == MR_REG*LANES, where LANES is the Acc lane count for token S