Struct gd32vf103_pac::timer0::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 18 fields
    pub ctl0: CTL0,
    pub ctl1: CTL1,
    pub smcfg: SMCFG,
    pub dmainten: DMAINTEN,
    pub intf: INTF,
    pub swevg: SWEVG,
    pub chctl2: CHCTL2,
    pub cnt: CNT,
    pub psc: PSC,
    pub car: CAR,
    pub crep: CREP,
    pub ch0cv: CH0CV,
    pub ch1cv: CH1CV,
    pub ch2cv: CH2CV,
    pub ch3cv: CH3CV,
    pub cchp: CCHP,
    pub dmacfg: DMACFG,
    pub dmatb: DMATB,
    /* private fields */

}
Expand description

Register block

Fields§

§ctl0: CTL0

0x00 - control register 0

§ctl1: CTL1

0x04 - control register 1

§smcfg: SMCFG

0x08 - slave mode configuration register

§dmainten: DMAINTEN

0x0c - DMA/Interrupt enable register

§intf: INTF

0x10 - Interrupt flag register

§swevg: SWEVG

0x14 - Software event generation register

§chctl2: CHCTL2

0x20 - Channel control register 2

§cnt: CNT

0x24 - counter

§psc: PSC

0x28 - prescaler

§car: CAR

0x2c - Counter auto reload register

§crep: CREP

0x30 - Counter repetition register

§ch0cv: CH0CV

0x34 - Channel 0 capture/compare value register

§ch1cv: CH1CV

0x38 - Channel 1 capture/compare value register

§ch2cv: CH2CV

0x3c - Channel 2 capture/compare value register

§ch3cv: CH3CV

0x40 - Channel 3 capture/compare value register

§cchp: CCHP

0x44 - channel complementary protection register

§dmacfg: DMACFG

0x48 - DMA configuration register

§dmatb: DMATB

0x4c - DMA transfer buffer register

Implementations§

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impl RegisterBlock

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pub const fn chctl0_input(&self) -> &CHCTL0_INPUT

0x18 - Channel control register 0 (input mode)

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pub const fn chctl0_output(&self) -> &CHCTL0_OUTPUT

0x18 - Channel control register 0 (output mode)

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pub const fn chctl1_input(&self) -> &CHCTL1_INPUT

0x1c - Channel control register 1 (input mode)

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pub const fn chctl1_output(&self) -> &CHCTL1_OUTPUT

0x1c - Channel control register 1 (output mode)

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