[−][src]Type Definition gd32vf103_pac::dma1::ch1ctl::W
type W = W<u32, CH1CTL>;
Writer for register CH1CTL
Implementations
impl W
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pub fn chen(&mut self) -> CHEN_W<'_>
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Bit 0 - Channel enable
pub fn ftfie(&mut self) -> FTFIE_W<'_>
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Bit 1 - Enable bit for channel full transfer finish interrupt
pub fn htfie(&mut self) -> HTFIE_W<'_>
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Bit 2 - Enable bit for channel half transfer finish interrupt
pub fn errie(&mut self) -> ERRIE_W<'_>
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Bit 3 - Enable bit for channel error interrupt
pub fn dir(&mut self) -> DIR_W<'_>
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Bit 4 - Transfer direction
pub fn cmen(&mut self) -> CMEN_W<'_>
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Bit 5 - Circular mode enable
pub fn pnaga(&mut self) -> PNAGA_W<'_>
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Bit 6 - Next address generation algorithm of peripheral
pub fn mnaga(&mut self) -> MNAGA_W<'_>
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Bit 7 - Next address generation algorithm of memory
pub fn pwidth(&mut self) -> PWIDTH_W<'_>
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Bits 8:9 - Transfer data size of peripheral
pub fn mwidth(&mut self) -> MWIDTH_W<'_>
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Bits 10:11 - Transfer data size of memory
pub fn prio(&mut self) -> PRIO_W<'_>
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Bits 12:13 - Priority level
pub fn m2m(&mut self) -> M2M_W<'_>
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Bit 14 - Memory to Memory Mode