Struct gd32f1x0_hal::pac::dma::RegisterBlock
source · [−]#[repr(C)]pub struct RegisterBlock {Show 30 fields
pub intf: Reg<INTF_SPEC>,
pub intc: Reg<INTC_SPEC>,
pub ch0ctl: Reg<CH0CTL_SPEC>,
pub ch0cnt: Reg<CH0CNT_SPEC>,
pub ch0paddr: Reg<CH0PADDR_SPEC>,
pub ch0maddr: Reg<CH0MADDR_SPEC>,
pub ch1ctl: Reg<CH1CTL_SPEC>,
pub ch1cnt: Reg<CH1CNT_SPEC>,
pub ch1paddr: Reg<CH1PADDR_SPEC>,
pub ch1maddr: Reg<CH1MADDR_SPEC>,
pub ch2ctl: Reg<CH2CTL_SPEC>,
pub ch2cnt: Reg<CH2CNT_SPEC>,
pub ch2paddr: Reg<CH2PADDR_SPEC>,
pub ch2maddr: Reg<CH2MADDR_SPEC>,
pub ch3ctl: Reg<CH3CTL_SPEC>,
pub ch3cnt: Reg<CH3CNT_SPEC>,
pub ch3paddr: Reg<CH3PADDR_SPEC>,
pub ch3maddr: Reg<CH3MADDR_SPEC>,
pub ch4ctl: Reg<CH4CTL_SPEC>,
pub ch4cnt: Reg<CH4CNT_SPEC>,
pub ch4paddr: Reg<CH4PADDR_SPEC>,
pub ch4maddr: Reg<CH4MADDR_SPEC>,
pub ch5ctl: Reg<CH5CTL_SPEC>,
pub ch5cnt: Reg<CH5CNT_SPEC>,
pub ch5paddr: Reg<CH5PADDR_SPEC>,
pub ch5maddr: Reg<CH5MADDR_SPEC>,
pub ch6ctl: Reg<CH6CTL_SPEC>,
pub ch6cnt: Reg<CH6CNT_SPEC>,
pub ch6paddr: Reg<CH6PADDR_SPEC>,
pub ch6maddr: Reg<CH6MADDR_SPEC>,
/* private fields */
}
Expand description
Register block
Fields
intf: Reg<INTF_SPEC>
0x00 - DMA interrupt flag register (DMA_INTF)
intc: Reg<INTC_SPEC>
0x04 - DMA interrupt flag clear register (DMA_INTC)
ch0ctl: Reg<CH0CTL_SPEC>
0x08 - DMA channel configuration register (DMA_CH0CTL0)
ch0cnt: Reg<CH0CNT_SPEC>
0x0c - DMA channel 0 counter register
ch0paddr: Reg<CH0PADDR_SPEC>
0x10 - DMA channel 0 peripheral base address register
ch0maddr: Reg<CH0MADDR_SPEC>
0x14 - DMA channel 0 memory base address register
ch1ctl: Reg<CH1CTL_SPEC>
0x1c - DMA channel configuration register (DMA_CH1CTL0)
ch1cnt: Reg<CH1CNT_SPEC>
0x20 - DMA channel 1 counter register
ch1paddr: Reg<CH1PADDR_SPEC>
0x24 - DMA channel 1 peripheral base address register
ch1maddr: Reg<CH1MADDR_SPEC>
0x28 - DMA channel 1 memory base address register
ch2ctl: Reg<CH2CTL_SPEC>
0x30 - DMA channel configuration register (DMA_CH2CTL0)
ch2cnt: Reg<CH2CNT_SPEC>
0x34 - DMA channel 2 counter register
ch2paddr: Reg<CH2PADDR_SPEC>
0x38 - DMA channel 2 peripheral base address register
ch2maddr: Reg<CH2MADDR_SPEC>
0x3c - DMA channel 2 memory base address register
ch3ctl: Reg<CH3CTL_SPEC>
0x44 - DMA channel configuration register (DMA_CH3CTL0)
ch3cnt: Reg<CH3CNT_SPEC>
0x48 - DMA channel 3 counter register
ch3paddr: Reg<CH3PADDR_SPEC>
0x4c - DMA channel 3 peripheral base address register
ch3maddr: Reg<CH3MADDR_SPEC>
0x50 - DMA channel 3 memory base address register
ch4ctl: Reg<CH4CTL_SPEC>
0x58 - DMA channel configuration register (DMA_CH4CTL0)
ch4cnt: Reg<CH4CNT_SPEC>
0x5c - DMA channel 4 counter register
ch4paddr: Reg<CH4PADDR_SPEC>
0x60 - DMA channel 4 peripheral base address register
ch4maddr: Reg<CH4MADDR_SPEC>
0x64 - DMA channel 4 memory base address register
ch5ctl: Reg<CH5CTL_SPEC>
0x6c - DMA channel configuration register (DMA_CH5CTL0)
ch5cnt: Reg<CH5CNT_SPEC>
0x70 - DMA channel 5 counter register
ch5paddr: Reg<CH5PADDR_SPEC>
0x74 - DMA channel 5 peripheral base address register
ch5maddr: Reg<CH5MADDR_SPEC>
0x78 - DMA channel 5 memory base address register
ch6ctl: Reg<CH6CTL_SPEC>
0x80 - DMA channel configuration register (DMA_CH6CTL0)
ch6cnt: Reg<CH6CNT_SPEC>
0x84 - DMA channel 6 counter register
ch6paddr: Reg<CH6PADDR_SPEC>
0x88 - DMA channel 6 peripheral base address register
ch6maddr: Reg<CH6MADDR_SPEC>
0x8c - DMA channel 6 memory base address register
Auto Trait Implementations
impl !RefUnwindSafe for RegisterBlock
impl Send for RegisterBlock
impl !Sync for RegisterBlock
impl Unpin for RegisterBlock
impl UnwindSafe for RegisterBlock
Blanket Implementations
sourceimpl<T> BorrowMut<T> for T where
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
const: unstable · sourcefn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more