Struct gd32f1x0_hal::pac::timer1::RegisterBlock[−][src]

#[repr(C)]
pub struct RegisterBlock {
Show fields
    pub ctl0: Reg<CTL0_SPEC>,
    pub ctl1: Reg<CTL1_SPEC>,
    pub smcfg: Reg<SMCFG_SPEC>,
    pub dmainten: Reg<DMAINTEN_SPEC>,
    pub intf: Reg<INTF_SPEC>,
    pub swevg: Reg<SWEVG_SPEC>,
    pub chctl2: Reg<CHCTL2_SPEC>,
    pub cnt: Reg<CNT_SPEC>,
    pub psc: Reg<PSC_SPEC>,
    pub car: Reg<CAR_SPEC>,
    pub ch0cv: Reg<CH0CV_SPEC>,
    pub ch1cv: Reg<CH1CV_SPEC>,
    pub ch2cv: Reg<CH2CV_SPEC>,
    pub ch3cv: Reg<CH3CV_SPEC>,
    pub dmacfg: Reg<DMACFG_SPEC>,
    pub dmatb: Reg<DMATB_SPEC>,
    // some fields omitted

}
Expand description

Register block

Fields

ctl0: Reg<CTL0_SPEC>
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0x00 - control register 0

ctl1: Reg<CTL1_SPEC>
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0x04 - control register 1

smcfg: Reg<SMCFG_SPEC>
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0x08 - Slave mode configuration register

dmainten: Reg<DMAINTEN_SPEC>
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0x0c - DMA and interrupt enable register

intf: Reg<INTF_SPEC>
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0x10 - interrupt flag register

swevg: Reg<SWEVG_SPEC>
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0x14 - event generation register

chctl2: Reg<CHCTL2_SPEC>
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0x20 - Channel control register 2

cnt: Reg<CNT_SPEC>
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0x24 - Counter register

psc: Reg<PSC_SPEC>
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0x28 - Prescaler register

car: Reg<CAR_SPEC>
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0x2c - Counter auto reload register

ch0cv: Reg<CH0CV_SPEC>
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0x34 - Channel 0 capture/compare value register

ch1cv: Reg<CH1CV_SPEC>
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0x38 - Channel 1 capture/compare value register

ch2cv: Reg<CH2CV_SPEC>
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0x3c - Channel 2 capture/compare value registerV

ch3cv: Reg<CH3CV_SPEC>
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0x40 - Channel 3 capture/compare value register

dmacfg: Reg<DMACFG_SPEC>
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0x48 - DMA configuration register

dmatb: Reg<DMATB_SPEC>
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0x4c - DMA Transfer buffer register

Implementations

impl RegisterBlock[src]

pub fn chctl0_input(&self) -> &Reg<CHCTL0_INPUT_SPEC>[src]

0x18 - Channel control register 0 (input mode)

pub fn chctl0_output(&self) -> &Reg<CHCTL0_OUTPUT_SPEC>[src]

0x18 - Channel control register 0 (output mode)

pub fn chctl1_input(&self) -> &Reg<CHCTL1_INPUT_SPEC>[src]

0x1c - Channel control register 1 (input mode)

pub fn chctl1_output(&self) -> &Reg<CHCTL1_OUTPUT_SPEC>[src]

0x1c - Channel control register 1 (output mode)

Auto Trait Implementations

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    T: 'static + ?Sized, [src]

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    T: ?Sized, [src]

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impl<T> From<T> for T[src]

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impl<T, U> Into<U> for T where
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pub fn into(self) -> U[src]

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impl<T, U> TryFrom<U> for T where
    U: Into<T>, [src]

type Error = Infallible

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pub fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>[src]

Performs the conversion.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, [src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.

pub fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>[src]

Performs the conversion.