Enum gd32f1x0_hal::pac::timer0::chctl1_output::CH3COMCTL_A [−][src]
#[repr(u8)] pub enum CH3COMCTL_A { FROZEN, ACTIVEONMATCH, INACTIVEONMATCH, TOGGLE, FORCEINACTIVE, FORCEACTIVE, PWMMODE0, PWMMODE1, }
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Channel 3 compare output control
Value on reset: 0
Variants
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0: The comparison between the output compare register CHyCV and the counter CNT has no effect on the outputs
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1: Set channel to active level on match. OxCPRE signal is forced high when the counter matches the capture/compare register CHyCV
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2: Set channel to inactive level on match. OxCPRE signal is forced low when the counter matches the capture/compare register CHyCV
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3: OxCPRE toggles when CNT=CHyCV
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4: OxCPRE is forced low
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5: OxCPRE is forced high
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6: In upcounting, channel is active as long as CNT<CHyCV else inactive. In downcounting, channel is inactive as long as CNT>CHyCV else active
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7: Inversely to PwmMode0
Trait Implementations
impl Clone for CH3COMCTL_A
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impl Clone for CH3COMCTL_A
[src]pub fn clone(&self) -> CH3COMCTL_A
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pub fn clone(&self) -> CH3COMCTL_A
[src]Returns a copy of the value. Read more
fn clone_from(&mut self, source: &Self)
1.0.0[src]
fn clone_from(&mut self, source: &Self)
1.0.0[src]Performs copy-assignment from source
. Read more
impl Debug for CH3COMCTL_A
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impl Debug for CH3COMCTL_A
[src]impl PartialEq<CH3COMCTL_A> for CH3COMCTL_A
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impl PartialEq<CH3COMCTL_A> for CH3COMCTL_A
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