Module gd32f1x0_hal::pac::timer0::chctl1_output [−][src]
Expand description
Channel control register 1 (output mode)
Structs
| CH2COMCEN_W | Field |
| CH2COMCTL_W | Field |
| CH2COMFEN_W | Field |
| CH2COMSEN_W | Field |
| CH2MS_W | Field |
| CH3COMCEN_R | Field |
| CH3COMCEN_W | Field |
| CH3COMCTL_R | Field |
| CH3COMCTL_W | Field |
| CH3COMFEN_R | Field |
| CH3COMFEN_W | Field |
| CH3COMSEN_R | Field |
| CH3COMSEN_W | Field |
| CH3MS_R | Field |
| CH3MS_W | Field |
| CHCTL1_OUTPUT_SPEC | Channel control register 1 (output mode) |
| R | Register |
| W | Register |
Enums
| CH3COMCEN_A | Channel 3 output compare clear enable |
| CH3COMCTL_A | Channel 3 compare output control |
| CH3COMFEN_A | Channel 3 output compare fast enable |
| CH3COMSEN_A | Channel 3 output compare shadow enable |
| CH3MS_A | Channel 3 mode selection |
Type Definitions
| CH2COMCEN_A | Channel 2 output compare clear enable |
| CH2COMCEN_R | Field |
| CH2COMCTL_A | Channel 2 compare output control |
| CH2COMCTL_R | Field |
| CH2COMFEN_A | Channel 2 output compare fast enable |
| CH2COMFEN_R | Field |
| CH2COMSEN_A | Channel 2 output compare shadow enable |
| CH2COMSEN_R | Field |
| CH2MS_A | Channel 2 mode selection |
| CH2MS_R | Field |