Type Definition gd32f1::gd32f130::dma::ch0ctl0::W

type W = W<u32, CH0CTL0>;

Writer for register CH0CTL0

Implementations

impl W

pub fn chen(&mut self) -> CHEN_W<'_>

Bit 0 - Channel enable

pub fn ftfie(&mut self) -> FTFIE_W<'_>

Bit 1 - Enable bit for full transfer finish interrupt

pub fn htfie(&mut self) -> HTFIE_W<'_>

Bit 2 - Enable bit for half transfer finish interrupt

pub fn taeie(&mut self) -> TAEIE_W<'_>

Bit 3 - Enable bit for tranfer access error interrupt

pub fn dir(&mut self) -> DIR_W<'_>

Bit 4 - Transfer mode

pub fn cmen(&mut self) -> CMEN_W<'_>

Bit 5 - Circular mode enable

pub fn pnaga(&mut self) -> PNAGA_W<'_>

Bit 6 - Next address generation algorithm of peripheral

pub fn mnaga(&mut self) -> MNAGA_W<'_>

Bit 7 - Next address generation algorithm of memory

pub fn pwidth(&mut self) -> PWIDTH_W<'_>

Bits 8:9 - Transfer data size of peripheral

pub fn mwidth(&mut self) -> MWIDTH_W<'_>

Bits 10:11 - Transfer data size of memory

pub fn prio(&mut self) -> PRIO_W<'_>

Bits 12:13 - Priority Level of this channel

pub fn m2m(&mut self) -> M2M_W<'_>

Bit 14 - Memory to memory mode