pub struct DmaController { /* private fields */ }Expand description
The two PC/AT 8237 DMA controllers, serviced one unit per device request.
Models address/count registers, AT page registers, masks, transfer direction, auto-initialization and terminal count. Address/count accesses share one low/high flip-flop per controller. Channel 4 is the cascade and transfers no device data. Only memory-to-device transfers are implemented.
This models register-visible transfer state, without bus arbitration, timing, memory-to-memory transfers or peripheral-to-memory writes. Demand, single and block modes all service one unit per call; cascade mode does not transfer.
Implementations§
Source§impl DmaController
impl DmaController
Sourcepub fn ports(&self) -> &[PortRange]
pub fn ports(&self) -> &[PortRange]
I/O ports decoded by the controllers and their seven AT page registers.
Sourcepub fn outb(&mut self, port: u16, value: u8)
pub fn outb(&mut self, port: u16, value: u8)
Write an 8237 register or AT page register. Unknown ports ignore writes.
Sourcepub fn inb(&mut self, port: u16) -> u8
pub fn inb(&mut self, port: u16) -> u8
Read a current address/count, page or status register. Status reads clear terminal-count flags; other unsupported reads return FFh.
Sourcepub fn transfer(
&mut self,
request: DmaRequest,
memory: &ConventionalMemory,
) -> Result<Option<DmaUnit>>
pub fn transfer( &mut self, request: DmaRequest, memory: &ConventionalMemory, ) -> Result<Option<DmaUnit>>
Read one DMA unit and advance the channel only after memory access
succeeds. Masked, disabled, exhausted or incompatible requests return
Ok(None) without changing channel state.
Byte channels wrap within a 64 KiB page. Word channels shift their 16-bit address by one, ignore page bit zero and wrap within 128 KiB. Count FFFFh means 65,536 units. Terminal count either reloads the base registers in auto-init mode or stops the channel until reprogrammed.