Struct DeviceS2KernelMatrix 

pub struct DeviceS2KernelMatrix {
    pub rows: usize,
    pub cols: usize,
    pub ld: usize,
    pub col_major_dev: CudaSlice<f64>,
    pub stream: Arc<CudaStream>,
}

Device-resident (rows × cols) matrix in column-major layout with leading dimension ld ≥ rows. The slice holds ld * cols f64 elements; entry (i, j) lives at col_major_dev[j * ld + i].

On non-Linux builds the type is intentionally a host shadow so the surrounding orchestration compiles without cudarc.

Fields

rows: usize

cols: usize

ld: usize

col_major_dev: CudaSlice<f64>

stream: Arc<CudaStream>

Implementations

impl DeviceS2KernelMatrix

pub fn to_host_array(&self) -> Result<Array2<f64>, GpuError>

Copy the device matrix back to the host as a regular ndarray (rows × cols) row-major view. Convenience for tests + parity comparisons; production paths should keep the matrix resident.

The device matrix is (ld × cols) column-major; the host wants (rows × cols) row-major. Two costs dominate this round-trip on the real V100:

1. the device→host copy of the full ld·cols·8 B payload, and
2. the column-major→row-major transpose. On Linux the dtoh is staged through a cacheable pinned host buffer (see [PinnedF64]) so the DMA runs at full PCIe bandwidth (~10 GB/s) instead of the ~1.3 GB/s the driver achieves staging a pageable destination, and the subsequent host reads during the transpose hit L1/L2 normally (unlike write-combined pinned memory). The transpose itself is the parallel cache-blocked [col_major_to_row_major_parallel].

pub fn copy_to_host_col_major(&self, dst: &mut [f64]) -> Result<(), GpuError>

Copy the underlying (ld × cols) column-major payload to a caller-provided buffer. Used by to_host_array and by the device-resident cuSOLVER consumer when it needs to extract the coefficient vector.