Enum DispatchOp 

pub enum DispatchOp {
    Gemm {
        m: usize,
        n: usize,
        k: usize,
    },
    BatchedGemm {
        batch: usize,
        m: usize,
        n: usize,
        k: usize,
    },
    Potrf {
        p: usize,
        batch: usize,
    },
    SmallDenseBatchedPotrf {
        p: usize,
        batch: usize,
    },
    Trsm {
        m: usize,
        n: usize,
    },
    Gemv {
        m: usize,
        k: usize,
    },
    XtDiagX {
        n: usize,
        p: usize,
    },
    XtDiagY {
        n: usize,
        px: usize,
        q: usize,
    },
    JointHessian2x2 {
        n: usize,
        pa: usize,
        pb: usize,
    },
}

Discriminator used by route_through_gpu to apply the right size threshold from super::policy::GpuDispatchPolicy.

Variants

Gemm

Generic matrix-matrix product with the given output dims and reduction depth.

Fields

m: usize

n: usize

k: usize

BatchedGemm

Batch of independent matrix-matrix products.

Fields

batch: usize

m: usize

n: usize

k: usize

Potrf

Dense Cholesky factorization.

Fields

p: usize

batch: usize

SmallDenseBatchedPotrf

Batched small-dense Cholesky factorization where each block has the same small width p (≲ 32) but the batch is large. Routed through cusolverDnDpotrfBatched and kept device-resident for downstream triangular solves (Arrow-Schur, Stage-3 PIRLS).

Fields

p: usize

batch: usize

Trsm

Triangular matrix solve.

Fields

m: usize

n: usize

Gemv

Matrix-vector (or matrix · single-column) product.

Fields

m: usize

k: usize

XtDiagX

Xᵀ · diag(w) · X reduction with n rows and p columns.

Fields

n: usize

p: usize

XtDiagY

Xᵀ · diag(w) · Y reduction; px and q are the design and response widths.

Fields

n: usize

px: usize

q: usize

JointHessian2x2

2×2 joint Hessian block with two design widths.

Fields

n: usize

pa: usize

pb: usize

Implementations

impl DispatchOp

pub const fn flops(self) -> u128

Conservative flop estimate used for the generic gemm_min_flops gate.

pub fn admissible_under_any_policy(self) -> bool

True when SOME reachable Auto dispatch policy could admit this op.

Pre-probe Auto size gate (the CUDA startup-tax ordering fix): evaluated with the MOST PERMISSIVE values any production policy can carry — the calibration crossover floors (GpuDispatchPolicy::MIN_CALIBRATABLE_GEMM_FLOPS, GpuDispatchPolicy::MIN_CALIBRATABLE_POTRF_P) for the calibrated fields, and the GpuDispatchPolicy::default values for the small-dense-batched-POTRF fields, which calibration::calibrate_device never adjusts. A false here means EVERY reachable policy’s route_through_gpu admission would also refuse, so the caller may return to the CPU path WITHOUT resolving GPU availability — i.e. without triggering the device probe and its per-GPU cuDevicePrimaryCtxRetain context creation. A true decides nothing: the probed runtime’s real policy still gates the op exactly as before.

Trait Implementations

impl Clone for DispatchOp

fn clone(&self) -> DispatchOp

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for DispatchOp

impl Debug for DispatchOp

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.