Enum F32LinearAccumulation 

pub enum F32LinearAccumulation {
    Scalar,
    Lanes4,
    Lanes8,
    FusedLanes4,
    FusedLanes8,
    Accelerate,
    AccelerateRowInvariant,
    AccelerateBiasSeeded,
    AccelerateBiasSeededRowInvariant,
    WidenedF64,
}

Reduction order used by linear_with_accumulation.

The scalar order is the f32 reference used by production code. The lane orders are retained so the CPU-fp32 fixture test can identify whether a BLAS-style partial reduction is responsible for a layer-level arithmetic divergence.

Variants

Scalar

One left-to-right f32 accumulator.

Lanes4

Four independent f32 partial accumulators, reduced in lane order.

Lanes8

Eight independent f32 partial accumulators, reduced in lane order.

FusedLanes4

Four FMA partial accumulators, reduced in lane order.

FusedLanes8

Eight FMA partial accumulators, reduced in lane order.

Accelerate

macOS Accelerate SGEMM, selected only by the CPU-fp32 parity harness.

On every other target, this deliberately falls back to Self::Scalar.

AccelerateRowInvariant

Self::Accelerate, with M = 1 calls pinned onto the M >= 2 GEMM kernel.

See Self::AccelerateBiasSeededRowInvariant for the streaming == offline rationale; this is the same pinning for the beta = 0 route (the codec’s RVQ projections).

AccelerateBiasSeeded

macOS Accelerate SGEMM over a bias-seeded output, issued with beta = 1.

This is the exact call slow_conv2d_update_output_frame makes for a convolution with a bias, and it differs from Self::Accelerate — which adds the bias after a beta = 0 product — whenever the BLAS blocks its reduction. Like the other lane orders, it exists so the CPU-fp32 fixture can attribute a convolution’s divergence; it falls back to Self::Scalar with a trailing bias on every non-macOS target.

AccelerateBiasSeededRowInvariant

Self::AccelerateBiasSeeded, with M = 1 calls pinned onto the M >= 2 GEMM kernel.

Accelerate routes M = 1 to a GEMV kernel whose reduction order differs from its (measured row-invariant) M >= 2 GEMM kernel. Seams whose streaming variant must equal whole-sequence decode bit-for-bit — the codec convolutions — need every M on the same kernel path, and accept drifting a single-frame call away from the oracle’s own GEMV bits to get it. Seams the ORACLE itself computes at M = 1 (the speaker-encoder embedding head) must NOT use this: the GEMV path is the oracle-matching one there.

WidenedF64

One f64 accumulator, narrowed to f32 only at the store.

Not a candidate for what the oracle did — it is an attribution probe. Every f32 lane order above is one guess at the oracle’s reduction; this one removes the reduction’s rounding entirely, so the residual it leaves at a seam is the part of that seam’s divergence that a reduction order cannot explain. See talker_layer_attribution.

Trait Implementations

impl Clone for F32LinearAccumulation

fn clone(&self) -> F32LinearAccumulation

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for F32LinearAccumulation

impl Debug for F32LinearAccumulation

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Eq for F32LinearAccumulation

impl PartialEq for F32LinearAccumulation

fn eq(&self, other: &F32LinearAccumulation) -> bool

Equality operator ==.

fn ne(&self, other: &Rhs) -> bool

Inequality operator !=.

impl StructuralPartialEq for F32LinearAccumulation