Struct Crc32C

Source

pub struct Crc32C(/* private fields */);

Expand description

Implementation of CRC32C (Castagnoli polynomial) to compute a 32-bit cyclic redundancy check (CRC) using Castagnoli polynomial

§Example

let crc = frozen_core::crc32::Crc32C::default();

let b0: [u8; 8] = *b"12345678";
let b1: [u8; 8] = *b"ABCDEFGH";
let b2: [u8; 8] = *b"abcdefgh";
let b3: [u8; 8] = *b"zyxwvuts";

assert_eq!(crc.crc(&b0), crc.crc(&b0));
assert_eq!(crc.crc_2x([&b0, &b1]),crc.crc_2x([&b0, &b1]));
assert_eq!(crc.crc_4x([&b0, &b1, &b2, &b3]),crc.crc_4x([&b0, &b1, &b2, &b3]));

Implementations§

Source §

impl Crc32C

Source

pub fn new() -> Self

Create a new instance of Crc32C

§CRC backend (Hardware vs Software)

When the new instance is created, we select the fastest available backend,

On x86_64 we use sse4.2 SIMD instructions when available
On aarch64 we use ARMv8 crc instructions when available
Otherwise, fallback to portable software implementation

Hardware acceleration is significantly faster than the software fallback, while both backend producing exact same CRC values

§Example

let crc = frozen_core::crc32::Crc32C::default();

let b0: [u8; 8] = *b"12345678";
let b1: [u8; 8] = *b"ABCDEFGH";
let b2: [u8; 8] = *b"abcdefgh";
let b3: [u8; 8] = *b"zyxwvuts";

assert_eq!(crc.crc(&b0), crc.crc(&b0));
assert_eq!(crc.crc_2x([&b0, &b1]),crc.crc_2x([&b0, &b1]));
assert_eq!(crc.crc_4x([&b0, &b1, &b2, &b3]),crc.crc_4x([&b0, &b1, &b2, &b3]));

Source

pub fn is_hardware_acceleration_available(&self) -> bool

Checks whether hardware acceleration is available at runtime

let crc = frozen_core::crc32::Crc32C::default();

#[cfg(target_arch = "x86_64")]
let expected = std::is_x86_feature_detected!("sse4.2");

#[cfg(target_arch = "aarch64")]
let expected = std::arch::is_aarch64_feature_detected!("crc");

assert_eq!(crc.is_hardware_acceleration_available(), expected);

Source

pub fn crc(&self, buf: &[u8]) -> u32

Compute CRC32C for given buf to generate 32-bit crc

NOTE: Length of buf must be a multiple of 8

At runtime we choose the fastest available backend,

x86_64: sse4.2 when available
aarch64: ArmV8 crc instruction when available
fallback: software castagnoli impl

All backends produce identical CRC32C values

§Example

let crc = frozen_core::crc32::Crc32C::default();

let b0: [u8; 8] = *b"12345678";
assert_eq!(crc.crc(&b0), crc.crc(&b0));

Source

pub fn crc_2x(&self, buffers: [&[u8]; 2]) -> [u32; 2]

Compute CRC32C for two bufs in parallel using Instruction Level Parallelism to generate 32-bit crc for each buf (mapped one-to-one)

NOTE: Length of each buf must be equal and a multiple of 8

At runtime we choose the fastest available backend,

x86_64: sse4.2 when available
aarch64: ArmV8 crc instruction when available
fallback: software castagnoli impl

All backends produce identical CRC32C values

§Example

let crc = frozen_core::crc32::Crc32C::default();

let b0: [u8; 8] = *b"12345678";
let b1: [u8; 8] = *b"ABCDEFGH";

assert_eq!(crc.crc_2x([&b0, &b1]),crc.crc_2x([&b0, &b1]));

Source

pub fn crc_4x(&self, buffers: [&[u8]; 4]) -> [u32; 4]

Compute CRC32C for four bufs in parallel using Instruction Level Parallelism to generate 32-bit crc for each buf (mapped one-to-one)

NOTE: Length of each buf must be equal and a multiple of 8

At runtime we choose the fastest available backend,

x86_64: sse4.2 when available
aarch64: ArmV8 crc instruction when available
fallback: software castagnoli impl

All backends produce identical CRC32C values

§Example

let crc = frozen_core::crc32::Crc32C::default();

let b0: [u8; 8] = *b"12345678";
let b1: [u8; 8] = *b"ABCDEFGH";
let b2: [u8; 8] = *b"abcdefgh";
let b3: [u8; 8] = *b"zyxwvuts";

assert_eq!(crc.crc_4x([&b0, &b1, &b2, &b3]),crc.crc_4x([&b0, &b1, &b2, &b3]));