#[non_exhaustive]#[repr(u16)]pub enum Feature {
Show 58 variants
Base = 0,
Fp16 = 1,
Bf16 = 2,
Lse = 3,
PAuth = 4,
Mte = 5,
Sve = 6,
Sme = 7,
Crypto = 8,
Tme = 9,
Trf = 10,
Wfxt = 11,
Frintts = 12,
Ls64 = 13,
Xs = 14,
Mops = 15,
Cssc = 16,
Rcpc3 = 17,
D128 = 18,
The = 19,
Lse128 = 20,
Sme2 = 21,
Lsui = 22,
Sve2p1 = 23,
Cpa = 24,
Cmpbr = 25,
I8mm = 26,
Fp8 = 27,
Lut = 28,
Lsfe = 29,
Faminmax = 30,
F16f32mm = 31,
F16mm = 32,
F8f16mm = 33,
F8f32mm = 34,
Hbc = 35,
PauthLr = 36,
SmeB16b16 = 37,
SmeF8f32 = 38,
SmeF8f16 = 39,
SmeF16f16 = 40,
SmeMop4 = 41,
SveB16b16 = 42,
Rprfm = 43,
F16f32dot = 44,
Sve2p2 = 45,
Sve2p3 = 46,
SveAes2 = 47,
Fprcvt = 48,
Tchange = 49,
Gcs = 50,
Chk = 51,
Pcdphint = 52,
Dgh = 53,
Clrbhb = 54,
Tev = 55,
AppleAmx = 56,
Gxf = 57,
}Expand description
A single architecture extension identity for per-encoding runtime gating.
One bit position per supported FEAT_* extension. Used by
crate::Code::feature and FeatureSet.
Variants (Non-exhaustive)§
This enum is marked as non-exhaustive
Base = 0
Base ISA — always available, never gated.
Fp16 = 1
Half-precision floating point (FEAT_FP16).
Bf16 = 2
BFloat16 (FEAT_BF16).
Lse = 3
Large System Extensions / atomics (FEAT_LSE).
PAuth = 4
Pointer authentication (FEAT_PAuth).
Mte = 5
Memory tagging (FEAT_MTE).
Sve = 6
Scalable Vector Extension (FEAT_SVE).
Sme = 7
Scalable Matrix Extension (FEAT_SME).
Crypto = 8
Cryptographic extensions (AES/SHA/SM3/SM4 family).
Tme = 9
Transactional Memory Extension (FEAT_TME).
Trf = 10
Trace synchronization barrier (FEAT_TRF).
Wfxt = 11
Wait-for-event/interrupt with timeout (FEAT_WFxT).
Frintts = 12
FP round-to-integer with rounding to 32/64-bit integers (FEAT_FRINTTS).
Ls64 = 13
Single-copy atomic 64-byte load/store (FEAT_LS64).
Xs = 14
Memory system non-XS qualifier for barriers (FEAT_XS): the DSB
<option>nXS variants.
Mops = 15
Memory Copy and Memory Set instructions (FEAT_MOPS): the CPYF*/CPY*
and SET*/SETG* families.
Cssc = 16
Common Short Sequence Compression (FEAT_CSSC): the ABS/CNT/CTZ
1-source forms and the SMAX/SMIN/UMAX/UMIN register- and
immediate-operand min/max forms.
Rcpc3 = 17
Release Consistent processor consistent, version 3 (FEAT_LRCPC3): the
SIMD&FP LDAPUR/STLUR (unscaled release/acquire) forms and the
LDIAPP/STILP ordered load/store-pair forms.
D128 = 18
128-bit system-register and translation support (FEAT_D128): the
MRRS/MSRR 128-bit system-register pair moves and the SYSP/TLBIP
system-pair operations.
The = 19
Translation Hardening Extension (FEAT_THE): the unprivileged
translation-enhanced load/store-pair forms LDTP/STTP (post/offset/pre)
and the non-temporal LDTNP/STTNP.
Lse128 = 20
128-bit Large System Extension atomics (FEAT_LSE128): the
LDCLRP/LDSETP/SWPP 128-bit atomic load-op-store-pair forms (with
their acquire/release ordering variants).
Sme2 = 21
SME2 multi-vector extension (FEAT_SME2): the multi-vector ZA-array
accumulate / multiply-into-ZA family (SMLALL/FMLAL/FMLA/… with
za.<T>[w8, <slice>{, vgx2|vgx4}] destinations) and the FTMOPA/STMOPA
outer-product forms.
Lsui = 22
Unprivileged Load Store (FEAT_LSUI): the quadword unprivileged
translation-enhanced load/store-pair forms LDTP/STTP (post/offset/pre)
and the non-temporal LDTNP/STTNP with Q data registers, plus the
unprivileged atomics — load/store-exclusive (LDTXR/LDATXR/STTXR/
STLTXR) and compare-and-swap (CAST/CASAT/CASLT/CASALT and the
pair CASPT/CASPAT/CASPLT/CASPALT).
Sve2p1 = 23
SVE2.1 / SME2.1 (FEAT_SVE2p1): the 128-bit-segment quadword permutes
(ZIPQ1/2, UZPQ1/2, TBLQ, TBXQ) and the 2-way SDOT/UDOT .h
(<Zda>.s, <Zn>.h, <Zm>.h{[idx]}) dot-product forms.
Cpa = 24
Checked Pointer Arithmetic (FEAT_CPA): the pointer-arithmetic
ADDPT/SUBPT forms — the SVE predicated/unpredicated .d vector forms
and the scalar ADDPT/SUBPT (and MADDPT/MSUBPT) base forms.
Cmpbr = 25
Compare and Branch (FEAT_CMPBR): the register/register and
register/immediate compare-and-branch forms CB<cc> (word/doubleword)
plus their byte (CBB<cc>) and halfword (CBH<cc>) register variants.
I8mm = 26
Int8 matrix multiply / mixed-sign dot product (FEAT_I8MM): the
Advanced SIMD USDOT/SUDOT byte dot products (vector and by-element).
Fp8 = 27
8-bit floating-point (FEAT_FP8 and the FP8DOT2/FP8DOT4/FP8FMA
sub-features): the Advanced SIMD FDOT (to single/half), FMLALB/
FMLALT and FMLALLBB/FMLALLBT/FMLALLTB/FMLALLTT FP8 widening
multiply-accumulate forms (vector and by-element).
Lut = 28
Lookup table (FEAT_LUT): the SVE LUTI2/LUTI4 vector lookup-table
reads — single- and two-register table forms with .b/.h element
variants, indexed by a vector-element selector (<Zm>[<index>]).
Lsfe = 29
Floating-point absolute maximum/minimum (FEAT_FAMINMAX): the Advanced
SIMD FAMAX/FAMIN vector forms (.4h/.8h/.2s/.4s/.2d).
Atomic floating-point in-memory instructions (FEAT_LSFE): the
LDF{ADD,MAX,MIN,MAXNM,MINNM} / STF* and BFloat16 LDBF*/STBF*
atomic float read-modify-write memory ops (H/S/D + BF16, a/l/al ordering).
Faminmax = 30
F16f32mm = 31
FP16-to-FP32 Advanced SIMD matrix multiply-accumulate (FEAT_F16F32MM):
the NEON FMMLA <Vd>.4S, <Vn>.8H, <Vm>.8H widening matrix product.
F16mm = 32
Non-widening half-precision Advanced SIMD matrix multiply-accumulate
(FEAT_F16MM): the NEON FMMLA <Vd>.8H, <Vn>.8H, <Vm>.8H.
F8f16mm = 33
FP8-to-half Advanced SIMD matrix multiply-accumulate (FEAT_F8F16MM):
the NEON FMMLA <Vd>.8H, <Vn>.16B, <Vm>.16B.
F8f32mm = 34
FP8-to-single Advanced SIMD matrix multiply-accumulate (FEAT_F8F32MM):
the NEON FMMLA <Vd>.4S, <Vn>.16B, <Vm>.16B.
Hbc = 35
Hinted conditional branches (FEAT_HBC): the consistent/hinted
conditional branch BC.<cond> <label> — the bit4 == 1 sibling of the
ordinary B.<cond> conditional-branch encoding.
PauthLr = 36
Pointer authentication using link register (FEAT_PAuth_LR): the
PC-relative return/authenticate branch forms RETAASPPC/RETABSPPC and
AUTIASPPC/AUTIBSPPC (<label>).
SmeB16b16 = 37
Non-widening BFloat16 (FEAT_SME_B16B16): the SME outer-product BMOPA/
BMOPS (.s) and BFMOPA/BFMOPS (.h) BFloat16 forms, plus the
BFMOP4A/BFMOP4S 4-source MOP4 BFloat16 variants.
SmeF8f32 = 38
FP8-to-single SME outer product (FEAT_SME_F8F32): the FMOPA /
FMOP4A forms with an FP8 (.b) source accumulating into an .s tile.
SmeF8f16 = 39
FP8-to-half SME outer product (FEAT_SME_F8F16): the FMOPA / FMOP4A
forms with an FP8 (.b) source accumulating into an .h tile.
SmeF16f16 = 40
Half-precision SME outer product (FEAT_SME_F16F16): the non-widening
FMOPA/FMOPS (.h) forms and the FMOP4A/FMOP4S (.h) MOP4 forms.
SmeMop4 = 41
Quarter-tile 4-source SME outer products (FEAT_SME_MOP4): the
FMOP4A/SMOP4A/… family with a {Zm, Zm+1} (and optional {Zn, Zn+1}) register-pair source replacing the governing predicates.
SveB16b16 = 42
Non-widening BFloat16 SVE arithmetic (FEAT_SVE_B16B16): the predicated
and unpredicated BFADD/BFSUB/BFMUL/BFMLA/BFMLS/BFMAX/BFMIN/
BFMAXNM/BFMINNM (.h) forms and the BFCLAMP (.h) three-source
clamp — all sharing the size==00 slot of the FP arithmetic encodings.
Rprfm = 43
Range prefetch memory (FEAT_RPRFM): the RPRFM <rprfop>, <Xm>, [<Xn|SP>] range-prefetch hint, encoded in the PRFM (register offset)
slot (size==11, opc==10) with option<1>==1 and word<11:10>==10.
F16f32dot = 44
FP16-to-FP32 Advanced SIMD half-precision dot-product accumulate to
single-precision (FEAT_F16F32DOT): the NEON FDOT <Vd>.<2s/4s>, <Vn>.<4h/8h>, <Vm>.<4h/8h> vector and <Vm>.2H[<index>] by-element forms.
Sve2p2 = 45
Scalable Vector Extension 2.2 (FEAT_SVE2p2): the predicated SQABS/
SQNEG zeroing (/z) forms and the FRINT32Z/X/FRINT64Z/X merging
(/m) round-to-integral forms added on top of the SVE2.1 baseline.
Sve2p3 = 46
Scalable Vector Extension 2.3 (FEAT_SVE2p3): the quadword pair add
(ADDQP) / add-subtract (ADDSUBP) unpredicated forms and the 2-way
UDOT/SDOT (.h <- .b) dot products.
SveAes2 = 47
SVE AES enhancements (FEAT_SVE_AES2): the multi-vector quadword AES
round forms AESE/AESD/AESEMC/AESDIMC ({ Zdn.b, ... }, { ... }, Zm.q[i]) and the polynomial multiply-long PMULL/PMLAL ({ Zd.q, Zd+1.q }, Zn.d, Zm.d).
Fprcvt = 48
Floating-point to/from integer conversion with differing register widths
(FEAT_FPRCVT): the scalar FCVT{N,P,M,Z,A}{S,U} and SCVTF/UCVTF
forms whose source and destination FP/SIMD register widths differ
(e.g. FCVTMS <Sd>, <Hn>, SCVTF <Dd>, <Sn>).
Tchange = 49
Translation-table change instructions (TCHANGEF/TCHANGEB): the
system-block TCHANGE{F,B} <Xt>, <Xn> (register) and TCHANGE{F,B} <Xt>, #<imm> (immediate) forms.
Gcs = 50
Guarded Control Stack (FEAT_GCS): the GCS stack-maintenance system ops
GCSPUSHM/GCSPOPM/GCSSS1/GCSSS2/GCSPUSHX/GCSPOPX/GCSPOPCX, the
GCSB DSYNC hint, the GCSSTR/GCSSTTR stores, and the TENTER guarded
transactional entry.
Chk = 51
Checked feature status (FEAT_CHK): the CHKFEAT <Xt> hint.
Pcdphint = 52
Producer/consumer data-placement hints (FEAT_PCDPHINT): the STSHH
(keep/strm), SHUH/SHUH PH, and STCPH cache-stashing hints.
Dgh = 53
Data Gathering Hint (FEAT_DGH): the DGH memory-gathering hint.
Clrbhb = 54
Clear Branch History (FEAT_CLRBHB): the CLRBHB branch-history-clear
hint.
Tev = 55
TIndex Exception-like Vector (FEAT_TEV): the TENTER #imm{, nb}
transactional/index-exception entry instruction.
AppleAmx = 56
Apple AMX matrix coprocessor (IMPLEMENTATION DEFINED; pre-M4 Apple
silicon A14–A17 / M1–M3). The 0x00201000-family micro-ops
(LDX/STX/LDZ/FMA64/MAC16/VECINT/MATFP/GENLUT/…). This is
not an Arm architectural extension and is not decoded by LLVM; the
encodings are reverse-engineered (corsix/amx). M4 and later replaced it
with the Arm-standard SME, which is covered by Feature::Sme. See
https://github.com/corsix/amx.
Gxf = 57
Apple Guarded Execution Feature (GXF; IMPLEMENTATION DEFINED). The
GENTER/GEXIT instructions that enter/exit Apple’s lateral “guarded”
exception levels (0x00201400 cluster). Not an Arm extension and not
decoded by LLVM; reverse-engineered from Apple-silicon research. See the
https://asahilinux.org/docs/hw/cpu/apple-instructions/ encoding notes
and https://blog.svenpeter.dev/posts/m1_sprr_gxf/ for GXF background.