Crate extract_rust_hdl_interface

generate_rust_hdl_module

This crate provides a extract_rust_hdl_interface function that extracts all the info you need to generate a rust-hdl module from a Verilog module.

The function does not actually generate code it just extracts the interface. It is mainly meant be used through the wrap_verilog! macro.

Structs

RustHdlModule

Represents a rust-hdl module.

Signal

Represents a signal in a rust-hdl module.

Enums

Direction

SignalType

The type of a signal.

Functions

extract_rust_hdl_interface

Extract all information needed to generate a wrapping rust-hdl module from a Verilog module.