Function tensor_load_l2 

pub unsafe fn tensor_load_l2(
    addr: usize,
    start: u8,
    rows: u8,
    id: bool,
    stride: u64,
)

Initiate an asynchronous TensorLoadL2Scp from memory into the shire L2 cache.

Identical to tensor_load in xs encoding and x31 convention, but targets CSR 0x85F (TensorLoadL2Scp) rather than 0x83F. The rows are loaded into the shire L2 without consuming any L1 scratchpad lines. Use this to prefetch A strips while the current k-loop FMA executes; the subsequent tensor_load for the same address will then complete from L2 rather than DRAM, removing A-DMA latency from the FMA critical path.

Parameters

• addr: 64-byte aligned virtual address of the first row in memory.
• start: L2 target line index.
• rows: rows to load minus one (0..=15).
• id: selects the wait event (false = LoadL2_0, true = LoadL2_1). Use LoadL2_1 when a tensor_load with id: false is also in flight.
• stride: row stride in bytes (64-byte aligned); placed in x31.

Call tensor_wait(TensorEvent::LoadL2_0) (or LoadL2_1 if id = true) before the scratchpad fill from the same address. Do not use CacheOp (event 6) – TensorLoadL2Scp requires events 2/3 per PRM Table 9-2.

Safety

Same constraints as tensor_load: addr must be aligned and within device memory; must be called from the primary hart.