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tensor_load_interleave16

et_kernel::tensor

Function tensor_load_interleave16 

Source 
pub unsafe fn tensor_load_interleave16(
    addr: usize,
    start: u8,
    rows: u8,
    id: bool,
    stride: u64,
)
Expand description

Initiate an asynchronous TensorLoadInterleave16 from memory into the L1 scratchpad.

Identical to tensor_load except that the hardware automatically interleaves consecutive fp16 row pairs during the DMA transfer, producing the 2-row-interleaved layout that tensor_fma16a32 expects in the scratchpad. This avoids a host-side pre-packing pass for A tiles when the source data is plain row-major fp16 in DRAM.

The distinction from tensor_load_b: TensorLoadInterleave16 writes to the L1 scratchpad (bit 52 = 0) and is suitable for A tiles passed to tensor_fma16a32 with tenb = false. The TenB register-file path has no hardware interleave mode; B must be pre-packed host-side.

§Parameters

  • addr: 64-byte aligned virtual address of the first row in memory.
  • start: L1 scratchpad starting line index (0..=47).
  • rows: number of rows to load minus one (ROWS field, 0..=15). Loads rows + 1 cache lines.
  • id: selects the TensorWait event (false = Load0, true = Load1).
  • stride: row stride in bytes (64-byte aligned); placed in x31.

§Safety

Same alignment and primary-hart constraints as tensor_load.