Module simd 

Packed-single (PS) SIMD intrinsics for 256-bit FP registers.

Provides simd::broadcast_ps, simd::fmul_ps_row, and simd::scale_c_row, encoded from esperanto-opc.h in the ET-SoC-1 binutils fork. Requires the f target feature (target-feature=+f); without it the module is empty. Hardware-verified on aifoundry3 (2026-09-18): all 1024 Minions produced correct results for FBCX.PS and FMUL.PS. Packed-single (PS) SIMD intrinsics for the ET-SoC-1 Minion FP register file.

The ET-SoC-1 PS extension operates on the 256-bit FP registers (f0..f31), treating each as a vector of eight single-precision (f32) lanes. PS instructions share the standard RISC-V FP register file and therefore require the f target feature to be enabled at compile time.

Enabling this module

The module is gated on cfg(target_feature = "f"). When building with .cargo/config.toml targeting riscv64gc-unknown-none-elf, the F extension is included in the target triple and the module is available without any additional flags. On a different target, add +f explicitly:

[target.riscv64gc-unknown-none-elf]
rustflags = ["-C", "target-feature=+f"]

Without +f the module is empty; callers must be similarly gated.

Register assignment for a 16-row C tile

A 16-row GEMM C tile occupies the full FP register file (f0..f31) in register pairs: row N maps to (f[2N], f[2N+1]). The broadcast scratch register for [broadcast_ps] and [fmul_ps_row] must not overlap with the pair being scaled.

For tiles of at most 14 rows, pass [PS_SCRATCH_DEFAULT] (f28) as scratch. For a full 16-row tile, rows 14 (f28/f29) and 15 (f30/f31) conflict with f28, so the caller must choose a different scratch register:

1. Spill the chosen scratch register to the stack (one FP register via fsw/fld with a suitable frame slot).
2. Call [broadcast_ps](alpha, scratch).
3. Call [fmul_ps_row] for the conflicting row.
4. Restore the scratch register from the stack.

Encodings

Source: gdb/include/opcode/esperanto-opc.h in the ET-SoC-1 binutils fork. All PS arithmetic instructions use the RISC-V custom-3 opcode space (0x7b).

Instruction	MATCH	Format	Notes
fmul.ps	0x1000_007b	R-type	fd = fs1 .* fs2 (element-wise). funct7=0x08, funct3=0.
fbc.ps	0x0000_000b	I-type	Load 4 B from rs1+imm, broadcast to all 8 lanes of fd. opcode=0x0b, funct3=0.
fbcx.ps	0x0000_300b	I-type	Broadcast GPR rs1 to all 8 lanes of fd; imm=0 fixed. opcode=0x0b, funct3=3.
fmvs.x.ps	0xe000_207b	R-type	Extract lane rs2[2:0] from PS register rs1 to GPR rd. funct7=0x70, funct3=2.

Constants

PS_SCRATCH_DEFAULT

Default PS broadcast scratch register (f28 / ft8).

Functions

broadcast_ps^⚠

Broadcast scalar to all eight lanes of PS register dest (0..=31).

fmul_ps_row^⚠

Scale the PS register pair for row by the pre-broadcast PS register scratch.

scale_c_row^⚠

Broadcast alpha into f[scratch], then scale the PS register pair for row.