#[repr(u8)]pub enum TensorEvent {
Load0 = 0,
Load1 = 1,
Fma = 7,
Store = 8,
}Expand description
Tensor co-processor synchronisation events for tensor_wait.
The four-bit EVENT field in the TensorWait xs register selects which
outstanding operation the hart waits for before the instruction retires.
Variants§
Load0 = 0
Completion of all TensorLoad operations issued with ID = 0.
Load1 = 1
Completion of all TensorLoad operations issued with ID = 1.
Fma = 7
Completion of all preceding TensorFMA operations; the FP register file holds the final accumulated C tile and may be read or stored.
Store = 8
Completion of all preceding TensorStore DMA transfers (PRM Table 9-2,
event code 8). Drains only the tensor store DMA, allowing the compiler
more freedom to reorder non-tensor memory accesses around it. Prefer
this over a full fence rw, rw when only tensor-store ordering is
required (e.g. confirming one tile is written before reusing FP registers
for the next tile in a pipelined loop).
Trait Implementations§
Source§impl Clone for TensorEvent
impl Clone for TensorEvent
Source§fn clone(&self) -> TensorEvent
fn clone(&self) -> TensorEvent
1.0.0 (const: unstable) · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read more