[−][src]Struct esp8266::slc::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub slc_conf0: SLC_CONF0,
    pub slc_int_raw: SLC_INT_RAW,
    pub slc_int_status: SLC_INT_STATUS,
    pub slc_int_ena: SLC_INT_ENA,
    pub slc_int_clr: SLC_INT_CLR,
    pub slc_rx_status: SLC_RX_STATUS,
    pub slc_rx_fifo_push: SLC_RX_FIFO_PUSH,
    pub slc_tx_status: SLC_TX_STATUS,
    pub slc_tx_fifo_pop: SLC_TX_FIFO_POP,
    pub slc_rx_link: SLC_RX_LINK,
    pub slc_tx_link: SLC_TX_LINK,
    pub slc_intvec_tohost: SLC_INTVEC_TOHOST,
    pub slc_token0: SLC_TOKEN0,
    pub slc_token1: SLC_TOKEN1,
    pub slc_conf1: SLC_CONF1,
    pub slc_state0: SLC_STATE0,
    pub slc_state1: SLC_STATE1,
    pub slc_bridge_conf: SLC_BRIDGE_CONF,
    pub slc_rx_eof_des_addr: SLC_RX_EOF_DES_ADDR,
    pub slc_tx_eof_des_addr: SLC_TX_EOF_DES_ADDR,
    pub slc_rx_eof_bfr_des_addr: SLC_RX_EOF_BFR_DES_ADDR,
    pub slc_ahb_test: SLC_AHB_TEST,
    pub slc_sdio_st: SLC_SDIO_ST,
    pub slc_rx_dscr_conf: SLC_RX_DSCR_CONF,
    pub slc_txlink_dscr: SLC_TXLINK_DSCR,
    pub slc_txlink_dscr_bf0: SLC_TXLINK_DSCR_BF0,
    pub slc_txlink_dscr_bf1: SLC_TXLINK_DSCR_BF1,
    pub slc_rxlink_dscr: SLC_RXLINK_DSCR,
    pub slc_rxlink_dscr_bf0: SLC_RXLINK_DSCR_BF0,
    pub slc_rxlink_dscr_bf1: SLC_RXLINK_DSCR_BF1,
    pub slc_date: SLC_DATE,
    pub slc_id: SLC_ID,
}

Register block

Fields

slc_conf0: SLC_CONF0

0x00 - SLC_CONF0

slc_int_raw: SLC_INT_RAW

0x04 - SLC_INT_RAW

slc_int_status: SLC_INT_STATUS

0x08 - SLC_INT_STATUS

slc_int_ena: SLC_INT_ENA

0x0c - SLC_INT_ENA

slc_int_clr: SLC_INT_CLR

0x10 - SLC_INT_CLR

slc_rx_status: SLC_RX_STATUS

0x14 - SLC_RX_STATUS

slc_rx_fifo_push: SLC_RX_FIFO_PUSH

0x18 - SLC_RX_FIFO_PUSH

slc_tx_status: SLC_TX_STATUS

0x1c - SLC_TX_STATUS

slc_tx_fifo_pop: SLC_TX_FIFO_POP

0x20 - SLC_TX_FIFO_POP

slc_rx_link: SLC_RX_LINK

0x24 - SLC_RX_LINK

slc_tx_link: SLC_TX_LINK

0x28 - SLC_TX_LINK

slc_intvec_tohost: SLC_INTVEC_TOHOST

0x2c - SLC_INTVEC_TOHOST

slc_token0: SLC_TOKEN0

0x30 - SLC_TOKEN0

slc_token1: SLC_TOKEN1

0x34 - SLC_TOKEN1

slc_conf1: SLC_CONF1

0x38 - SLC_CONF1

slc_state0: SLC_STATE0

0x3c - SLC_STATE0

slc_state1: SLC_STATE1

0x40 - SLC_STATE1

slc_bridge_conf: SLC_BRIDGE_CONF

0x44 - SLC_BRIDGE_CONF

slc_rx_eof_des_addr: SLC_RX_EOF_DES_ADDR

0x48 - SLC_RX_EOF_DES_ADDR

slc_tx_eof_des_addr: SLC_TX_EOF_DES_ADDR

0x4c - SLC_TX_EOF_DES_ADDR

slc_rx_eof_bfr_des_addr: SLC_RX_EOF_BFR_DES_ADDR

0x50 - SLC_RX_EOF_BFR_DES_ADDR

slc_ahb_test: SLC_AHB_TEST

0x54 - SLC_AHB_TEST

slc_sdio_st: SLC_SDIO_ST

0x58 - SLC_SDIO_ST

slc_rx_dscr_conf: SLC_RX_DSCR_CONF

0x5c - SLC_RX_DSCR_CONF

slc_txlink_dscr: SLC_TXLINK_DSCR

0x60 - SLC_TXLINK_DSCR

slc_txlink_dscr_bf0: SLC_TXLINK_DSCR_BF0

0x64 - SLC_TXLINK_DSCR_BF0

slc_txlink_dscr_bf1: SLC_TXLINK_DSCR_BF1

0x68 - SLC_TXLINK_DSCR_BF1

slc_rxlink_dscr: SLC_RXLINK_DSCR

0x6c - SLC_RXLINK_DSCR

slc_rxlink_dscr_bf0: SLC_RXLINK_DSCR_BF0

0x70 - SLC_RXLINK_DSCR_BF0

slc_rxlink_dscr_bf1: SLC_RXLINK_DSCR_BF1

0x74 - SLC_RXLINK_DSCR_BF1

slc_date: SLC_DATE

0x78 - SLC_DATE

slc_id: SLC_ID

0x7c - SLC_ID

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