[−][src]Module esp8266::spi::spi_clock

In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock.

Structs

SPI_CLKCNT_H_W	Write proxy for field `spi_clkcnt_H`
SPI_CLKCNT_L_W	Write proxy for field `spi_clkcnt_L`
SPI_CLKCNT_N_W	Write proxy for field `spi_clkcnt_N`
SPI_CLKDIV_PRE_W	Write proxy for field `spi_clkdiv_pre`
SPI_CLK_EQU_SYSCLK_W	Write proxy for field `spi_clk_equ_sysclk`

R	Reader of register SPI_CLOCK
SPI_CLKCNT_H_R	Reader of field `spi_clkcnt_H`
SPI_CLKCNT_L_R	Reader of field `spi_clkcnt_L`
SPI_CLKCNT_N_R	Reader of field `spi_clkcnt_N`
SPI_CLKDIV_PRE_R	Reader of field `spi_clkdiv_pre`
SPI_CLK_EQU_SYSCLK_R	Reader of field `spi_clk_equ_sysclk`
W	Writer for register SPI_CLOCK