Module esp8266::spi

SPI

Modules

spi_addr	In the master mode, it is the value of address in "address" phase.
spi_clock	In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock.
spi_cmd	In the master mode, it is the start bit of a single operation. Self-clear by hardware
spi_ctrl	SPI_CTRL
spi_ctrl2	spi_cs signal is delayed by 80MHz clock cycles
spi_pin	1: disable CS2; 0: spi_cs signal is from/to CS2 pin
spi_rd_status	In the slave mode, this register are the status register for the master to read out.
spi_slave	It is the synchronous reset signal of the module. This bit is self-cleared by hardware.
spi_slave1	In the slave mode, it is the length in bits for "write-status" and "read-status" operations. The register valueshall be (bit_num-1)
spi_slave2	In the slave mode, it is the length in spi_clk cycles "dummy" phase for "write-buffer" operations. The registervalue shall be (cycle_num-1)
spi_slave3	In slave mode, it is the value of "write-status" command
spi_user	This bit enable the "command" phase of an operation.
spi_user1	The length in bits of "address" phase. The register value shall be (bit_num-1)
spi_user2	The length in bits of "command" phase. The register value shall be (bit_num-1)
spi_w0	the data inside the buffer of the SPI module, byte 0
spi_w1	the data inside the buffer of the SPI module, byte 1
spi_w2	the data inside the buffer of the SPI module, byte 2
spi_w3	the data inside the buffer of the SPI module, byte 3
spi_w4	the data inside the buffer of the SPI module, byte 4
spi_w5	the data inside the buffer of the SPI module, byte 5
spi_w6	the data inside the buffer of the SPI module, byte 6
spi_w7	the data inside the buffer of the SPI module, byte 7
spi_w8	the data inside the buffer of the SPI module, byte 8
spi_w9	the data inside the buffer of the SPI module, byte 9
spi_w10	the data inside the buffer of the SPI module, byte 10
spi_w11	the data inside the buffer of the SPI module, byte 11
spi_w12	the data inside the buffer of the SPI module, byte 12
spi_w13	the data inside the buffer of the SPI module, byte 13
spi_w14	the data inside the buffer of the SPI module, byte 14
spi_w15	the data inside the buffer of the SPI module, byte 15
spi_wr_status	In the slave mode, this register are the status register for the master to write into.

Structs

RegisterBlock

Register block

Type Definitions

SPI_ADDR	In the master mode, it is the value of address in "address" phase.
SPI_CLOCK	In the master mode, 1: spi_clk is eqaul to 80MHz, 0: spi_clk is divided from 80 MHz clock.
SPI_CMD	In the master mode, it is the start bit of a single operation. Self-clear by hardware
SPI_CTRL	SPI_CTRL
SPI_CTRL2	spi_cs signal is delayed by 80MHz clock cycles
SPI_PIN	1: disable CS2; 0: spi_cs signal is from/to CS2 pin
SPI_RD_STATUS	In the slave mode, this register are the status register for the master to read out.
SPI_SLAVE	It is the synchronous reset signal of the module. This bit is self-cleared by hardware.
SPI_SLAVE1	In the slave mode, it is the length in bits for "write-status" and "read-status" operations. The register valueshall be (bit_num-1)
SPI_SLAVE2	In the slave mode, it is the length in spi_clk cycles "dummy" phase for "write-buffer" operations. The registervalue shall be (cycle_num-1)
SPI_SLAVE3	In slave mode, it is the value of "write-status" command
SPI_USER	This bit enable the "command" phase of an operation.
SPI_USER1	The length in bits of "address" phase. The register value shall be (bit_num-1)
SPI_USER2	The length in bits of "command" phase. The register value shall be (bit_num-1)
SPI_W0	the data inside the buffer of the SPI module, byte 0
SPI_W1	the data inside the buffer of the SPI module, byte 1
SPI_W2	the data inside the buffer of the SPI module, byte 2
SPI_W3	the data inside the buffer of the SPI module, byte 3
SPI_W4	the data inside the buffer of the SPI module, byte 4
SPI_W5	the data inside the buffer of the SPI module, byte 5
SPI_W6	the data inside the buffer of the SPI module, byte 6
SPI_W7	the data inside the buffer of the SPI module, byte 7
SPI_W8	the data inside the buffer of the SPI module, byte 8
SPI_W9	the data inside the buffer of the SPI module, byte 9
SPI_W10	the data inside the buffer of the SPI module, byte 10
SPI_W11	the data inside the buffer of the SPI module, byte 11
SPI_W12	the data inside the buffer of the SPI module, byte 12
SPI_W13	the data inside the buffer of the SPI module, byte 13
SPI_W14	the data inside the buffer of the SPI module, byte 14
SPI_W15	the data inside the buffer of the SPI module, byte 15
SPI_WR_STATUS	In the slave mode, this register are the status register for the master to write into.