Module conf0

UHCI configuration register

Structs

CONF0_SPEC

UHCI configuration register

Type Aliases

CLK_EN_R

Field CLK_EN reader - 1’b1: Force clock on for register. 1’b0: Support clock only when application writes registers.

CLK_EN_W

Field CLK_EN writer - 1’b1: Force clock on for register. 1’b0: Support clock only when application writes registers.

CRC_REC_EN_R

Field CRC_REC_EN reader - Set this bit to enable UHCI to receive the 16 bit CRC.

CRC_REC_EN_W

Field CRC_REC_EN writer - Set this bit to enable UHCI to receive the 16 bit CRC.

ENCODE_CRC_EN_R

Field ENCODE_CRC_EN reader - Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload.

ENCODE_CRC_EN_W

Field ENCODE_CRC_EN writer - Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload.

HEAD_EN_R

Field HEAD_EN reader - Set this bit to encode the data packet with a formatting header.

HEAD_EN_W

Field HEAD_EN writer - Set this bit to encode the data packet with a formatting header.

LEN_EOF_EN_R

Field LEN_EOF_EN reader - If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received.

LEN_EOF_EN_W

Field LEN_EOF_EN writer - If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received.

R

Register CONF0 reader

RX_RST_R

Field RX_RST reader - Write 1, then write 0 to this bit to reset encode state machine.

RX_RST_W

Field RX_RST writer - Write 1, then write 0 to this bit to reset encode state machine.

SEPER_EN_R

Field SEPER_EN reader - Set this bit to separate the data frame using a special char.

SEPER_EN_W

Field SEPER_EN writer - Set this bit to separate the data frame using a special char.

TX_RST_R

Field TX_RST reader - Write 1, then write 0 to this bit to reset decode state machine.

TX_RST_W

Field TX_RST writer - Write 1, then write 0 to this bit to reset decode state machine.

UART0_CE_R

Field UART0_CE reader - Set this bit to link up HCI and UART0.

UART0_CE_W

Field UART0_CE writer - Set this bit to link up HCI and UART0.

UART1_CE_R

Field UART1_CE reader - Set this bit to link up HCI and UART1.

UART1_CE_W

Field UART1_CE writer - Set this bit to link up HCI and UART1.

UART2_CE_R

Field UART2_CE reader - Set this bit to link up HCI and UART2.

UART2_CE_W

Field UART2_CE writer - Set this bit to link up HCI and UART2.

UART_IDLE_EOF_EN_R

Field UART_IDLE_EOF_EN reader - If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state.

UART_IDLE_EOF_EN_W

Field UART_IDLE_EOF_EN writer - If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state.

UART_RX_BRK_EOF_EN_R

Field UART_RX_BRK_EOF_EN reader - If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART.

UART_RX_BRK_EOF_EN_W

Field UART_RX_BRK_EOF_EN writer - If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART.

W

Register CONF0 writer