esp32s3

Struct SENSITIVE

Source 
pub struct SENSITIVE { /* private fields */ }
Expand description

SENSITIVE Peripheral

Implementations§

Source§

impl SENSITIVE

Source

pub const PTR: *const RegisterBlock = {0x600c1000 as *const sensitive::RegisterBlock}

Pointer to the register block

Source

pub const fn ptr() -> *const RegisterBlock

Return the pointer to the register block

Source

pub unsafe fn steal() -> Self

Steal an instance of this peripheral

§Safety

Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.

Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.

Methods from Deref<Target = RegisterBlock>§

Source

pub fn cache_dataarray_connect_0(&self) -> &CACHE_DATAARRAY_CONNECT_0

0x00 - Cache data array configuration register 0.

Source

pub fn cache_dataarray_connect_1(&self) -> &CACHE_DATAARRAY_CONNECT_1

0x04 - Cache data array configuration register 1.

Source

pub fn apb_peripheral_access_0(&self) -> &APB_PERIPHERAL_ACCESS_0

0x08 - APB peripheral configuration register 0.

Source

pub fn apb_peripheral_access_1(&self) -> &APB_PERIPHERAL_ACCESS_1

0x0c - APB peripheral configuration register 1.

Source

pub fn internal_sram_usage_0(&self) -> &INTERNAL_SRAM_USAGE_0

0x10 - Internal SRAM configuration register 0.

Source

pub fn internal_sram_usage_1(&self) -> &INTERNAL_SRAM_USAGE_1

0x14 - Internal SRAM configuration register 1.

Source

pub fn internal_sram_usage_2(&self) -> &INTERNAL_SRAM_USAGE_2

0x18 - Internal SRAM configuration register 2.

Source

pub fn internal_sram_usage_3(&self) -> &INTERNAL_SRAM_USAGE_3

0x1c - Internal SRAM configuration register 3.

Source

pub fn internal_sram_usage_4(&self) -> &INTERNAL_SRAM_USAGE_4

0x20 - Internal SRAM configuration register 4.

Source

pub fn retention_disable(&self) -> &RETENTION_DISABLE

0x24 - Retention configuration register.

Source

pub fn cache_tag_access_0(&self) -> &CACHE_TAG_ACCESS_0

0x28 - Cache tag configuration register 0.

Source

pub fn cache_tag_access_1(&self) -> &CACHE_TAG_ACCESS_1

0x2c - Cache tag configuration register 1.

Source

pub fn cache_mmu_access_0(&self) -> &CACHE_MMU_ACCESS_0

0x30 - Cache MMU configuration register 0.

Source

pub fn cache_mmu_access_1(&self) -> &CACHE_MMU_ACCESS_1

0x34 - Cache MMU configuration register 1.

Source

pub fn dma_apbperi_spi2_pms_constrain_0( &self, ) -> &DMA_APBPERI_SPI2_PMS_CONSTRAIN_0

0x38 - spi2 dma permission configuration register 0.

Source

pub fn dma_apbperi_spi2_pms_constrain_1( &self, ) -> &DMA_APBPERI_SPI2_PMS_CONSTRAIN_1

0x3c - spi2 dma permission configuration register 1.

Source

pub fn dma_apbperi_spi3_pms_constrain_0( &self, ) -> &DMA_APBPERI_SPI3_PMS_CONSTRAIN_0

0x40 - spi3 dma permission configuration register 0.

Source

pub fn dma_apbperi_spi3_pms_constrain_1( &self, ) -> &DMA_APBPERI_SPI3_PMS_CONSTRAIN_1

0x44 - spi3 dma permission configuration register 1.

Source

pub fn dma_apbperi_uhci0_pms_constrain_0( &self, ) -> &DMA_APBPERI_UHCI0_PMS_CONSTRAIN_0

0x48 - uhci0 dma permission configuration register 0.

Source

pub fn dma_apbperi_uhci0_pms_constrain_1( &self, ) -> &DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1

0x4c - uhci0 dma permission configuration register 1.

Source

pub fn dma_apbperi_i2s0_pms_constrain_0( &self, ) -> &DMA_APBPERI_I2S0_PMS_CONSTRAIN_0

0x50 - i2s0 dma permission configuration register 0.

Source

pub fn dma_apbperi_i2s0_pms_constrain_1( &self, ) -> &DMA_APBPERI_I2S0_PMS_CONSTRAIN_1

0x54 - i2s0 dma permission configuration register 1.

Source

pub fn dma_apbperi_i2s1_pms_constrain_0( &self, ) -> &DMA_APBPERI_I2S1_PMS_CONSTRAIN_0

0x58 - i2s1 dma permission configuration register 0.

Source

pub fn dma_apbperi_i2s1_pms_constrain_1( &self, ) -> &DMA_APBPERI_I2S1_PMS_CONSTRAIN_1

0x5c - i2s1 dma permission configuration register 1.

Source

pub fn dma_apbperi_mac_pms_constrain_0( &self, ) -> &DMA_APBPERI_MAC_PMS_CONSTRAIN_0

0x60 - mac dma permission configuration register 0.

Source

pub fn dma_apbperi_mac_pms_constrain_1( &self, ) -> &DMA_APBPERI_MAC_PMS_CONSTRAIN_1

0x64 - mac dma permission configuration register 1.

Source

pub fn dma_apbperi_backup_pms_constrain_0( &self, ) -> &DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0

0x68 - backup dma permission configuration register 0.

Source

pub fn dma_apbperi_backup_pms_constrain_1( &self, ) -> &DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1

0x6c - backup dma permission configuration register 1.

Source

pub fn dma_apbperi_aes_pms_constrain_0( &self, ) -> &DMA_APBPERI_AES_PMS_CONSTRAIN_0

0x70 - aes dma permission configuration register 0.

Source

pub fn dma_apbperi_aes_pms_constrain_1( &self, ) -> &DMA_APBPERI_AES_PMS_CONSTRAIN_1

0x74 - aes dma permission configuration register 1.

Source

pub fn dma_apbperi_sha_pms_constrain_0( &self, ) -> &DMA_APBPERI_SHA_PMS_CONSTRAIN_0

0x78 - sha dma permission configuration register 0.

Source

pub fn dma_apbperi_sha_pms_constrain_1( &self, ) -> &DMA_APBPERI_SHA_PMS_CONSTRAIN_1

0x7c - sha dma permission configuration register 1.

Source

pub fn dma_apbperi_adc_dac_pms_constrain_0( &self, ) -> &DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0

0x80 - adc_dac dma permission configuration register 0.

Source

pub fn dma_apbperi_adc_dac_pms_constrain_1( &self, ) -> &DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1

0x84 - adc_dac dma permission configuration register 1.

Source

pub fn dma_apbperi_rmt_pms_constrain_0( &self, ) -> &DMA_APBPERI_RMT_PMS_CONSTRAIN_0

0x88 - rmt dma permission configuration register 0.

Source

pub fn dma_apbperi_rmt_pms_constrain_1( &self, ) -> &DMA_APBPERI_RMT_PMS_CONSTRAIN_1

0x8c - rmt dma permission configuration register 1.

Source

pub fn dma_apbperi_lcd_cam_pms_constrain_0( &self, ) -> &DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0

0x90 - lcd_cam dma permission configuration register 0.

Source

pub fn dma_apbperi_lcd_cam_pms_constrain_1( &self, ) -> &DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1

0x94 - lcd_cam dma permission configuration register 1.

Source

pub fn dma_apbperi_usb_pms_constrain_0( &self, ) -> &DMA_APBPERI_USB_PMS_CONSTRAIN_0

0x98 - usb dma permission configuration register 0.

Source

pub fn dma_apbperi_usb_pms_constrain_1( &self, ) -> &DMA_APBPERI_USB_PMS_CONSTRAIN_1

0x9c - usb dma permission configuration register 1.

Source

pub fn dma_apbperi_lc_pms_constrain_0(&self) -> &DMA_APBPERI_LC_PMS_CONSTRAIN_0

0xa0 - lc dma permission configuration register 0.

Source

pub fn dma_apbperi_lc_pms_constrain_1(&self) -> &DMA_APBPERI_LC_PMS_CONSTRAIN_1

0xa4 - lc dma permission configuration register 1.

Source

pub fn dma_apbperi_sdio_pms_constrain_0( &self, ) -> &DMA_APBPERI_SDIO_PMS_CONSTRAIN_0

0xa8 - sdio dma permission configuration register 0.

Source

pub fn dma_apbperi_sdio_pms_constrain_1( &self, ) -> &DMA_APBPERI_SDIO_PMS_CONSTRAIN_1

0xac - sdio dma permission configuration register 1.

Source

pub fn dma_apbperi_pms_monitor_0(&self) -> &DMA_APBPERI_PMS_MONITOR_0

0xb0 - dma permission monitor configuration register 0.

Source

pub fn dma_apbperi_pms_monitor_1(&self) -> &DMA_APBPERI_PMS_MONITOR_1

0xb4 - dma permission monitor configuration register 1.

Source

pub fn dma_apbperi_pms_monitor_2(&self) -> &DMA_APBPERI_PMS_MONITOR_2

0xb8 - dma permission monitor configuration register 2.

Source

pub fn dma_apbperi_pms_monitor_3(&self) -> &DMA_APBPERI_PMS_MONITOR_3

0xbc - dma permission monitor configuration register 3.

Source

pub fn core_x_iram0_dram0_dma_split_line_constrain_0( &self, ) -> &CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0

0xc0 - sram split line configuration register 0

Source

pub fn core_x_iram0_dram0_dma_split_line_constrain_1( &self, ) -> &CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1

0xc4 - sram split line configuration register 1

Source

pub fn core_x_iram0_dram0_dma_split_line_constrain_2( &self, ) -> &CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2

0xc8 - sram split line configuration register 1

Source

pub fn core_x_iram0_dram0_dma_split_line_constrain_3( &self, ) -> &CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3

0xcc - sram split line configuration register 1

Source

pub fn core_x_iram0_dram0_dma_split_line_constrain_4( &self, ) -> &CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4

0xd0 - sram split line configuration register 1

Source

pub fn core_x_iram0_dram0_dma_split_line_constrain_5( &self, ) -> &CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5

0xd4 - sram split line configuration register 1

Source

pub fn core_x_iram0_pms_constrain_0(&self) -> &CORE_X_IRAM0_PMS_CONSTRAIN_0

0xd8 - corex iram0 permission configuration register 0

Source

pub fn core_x_iram0_pms_constrain_1(&self) -> &CORE_X_IRAM0_PMS_CONSTRAIN_1

0xdc - corex iram0 permission configuration register 0

Source

pub fn core_x_iram0_pms_constrain_2(&self) -> &CORE_X_IRAM0_PMS_CONSTRAIN_2

0xe0 - corex iram0 permission configuration register 1

Source

pub fn core_0_iram0_pms_monitor_0(&self) -> &CORE_0_IRAM0_PMS_MONITOR_0

0xe4 - core0 iram0 permission monitor configuration register 0

Source

pub fn core_0_iram0_pms_monitor_1(&self) -> &CORE_0_IRAM0_PMS_MONITOR_1

0xe8 - core0 iram0 permission monitor configuration register 1

Source

pub fn core_0_iram0_pms_monitor_2(&self) -> &CORE_0_IRAM0_PMS_MONITOR_2

0xec - core0 iram0 permission monitor configuration register 2

Source

pub fn core_1_iram0_pms_monitor_0(&self) -> &CORE_1_IRAM0_PMS_MONITOR_0

0xf0 - core1 iram0 permission monitor configuration register 0

Source

pub fn core_1_iram0_pms_monitor_1(&self) -> &CORE_1_IRAM0_PMS_MONITOR_1

0xf4 - core1 iram0 permission monitor configuration register 1

Source

pub fn core_1_iram0_pms_monitor_2(&self) -> &CORE_1_IRAM0_PMS_MONITOR_2

0xf8 - core1 iram0 permission monitor configuration register 2

Source

pub fn core_x_dram0_pms_constrain_0(&self) -> &CORE_X_DRAM0_PMS_CONSTRAIN_0

0xfc - corex dram0 permission configuration register 0

Source

pub fn core_x_dram0_pms_constrain_1(&self) -> &CORE_X_DRAM0_PMS_CONSTRAIN_1

0x100 - corex dram0 permission configuration register 1

Source

pub fn core_0_dram0_pms_monitor_0(&self) -> &CORE_0_DRAM0_PMS_MONITOR_0

0x104 - core0 dram0 permission monitor configuration register 0

Source

pub fn core_0_dram0_pms_monitor_1(&self) -> &CORE_0_DRAM0_PMS_MONITOR_1

0x108 - core0 dram0 permission monitor configuration register 1

Source

pub fn core_0_dram0_pms_monitor_2(&self) -> &CORE_0_DRAM0_PMS_MONITOR_2

0x10c - core0 dram0 permission monitor configuration register 2.

Source

pub fn core_0_dram0_pms_monitor_3(&self) -> &CORE_0_DRAM0_PMS_MONITOR_3

0x110 - core0 dram0 permission monitor configuration register 3.

Source

pub fn core_1_dram0_pms_monitor_0(&self) -> &CORE_1_DRAM0_PMS_MONITOR_0

0x114 - core1 dram0 permission monitor configuration register 0

Source

pub fn core_1_dram0_pms_monitor_1(&self) -> &CORE_1_DRAM0_PMS_MONITOR_1

0x118 - core1 dram0 permission monitor configuration register 1

Source

pub fn core_1_dram0_pms_monitor_2(&self) -> &CORE_1_DRAM0_PMS_MONITOR_2

0x11c - core1 dram0 permission monitor configuration register 2.

Source

pub fn core_1_dram0_pms_monitor_3(&self) -> &CORE_1_DRAM0_PMS_MONITOR_3

0x120 - core1 dram0 permission monitor configuration register 3.

Source

pub fn core_0_pif_pms_constrain_0(&self) -> &CORE_0_PIF_PMS_CONSTRAIN_0

0x124 - Core0 access peripherals permission configuration register 0.

Source

pub fn core_0_pif_pms_constrain_1(&self) -> &CORE_0_PIF_PMS_CONSTRAIN_1

0x128 - Core0 access peripherals permission configuration register 1.

Source

pub fn core_0_pif_pms_constrain_2(&self) -> &CORE_0_PIF_PMS_CONSTRAIN_2

0x12c - Core0 access peripherals permission configuration register 2.

Source

pub fn core_0_pif_pms_constrain_3(&self) -> &CORE_0_PIF_PMS_CONSTRAIN_3

0x130 - Core0 access peripherals permission configuration register 3.

Source

pub fn core_0_pif_pms_constrain_4(&self) -> &CORE_0_PIF_PMS_CONSTRAIN_4

0x134 - Core0 access peripherals permission configuration register 4.

Source

pub fn core_0_pif_pms_constrain_5(&self) -> &CORE_0_PIF_PMS_CONSTRAIN_5

0x138 - Core0 access peripherals permission configuration register 5.

Source

pub fn core_0_pif_pms_constrain_6(&self) -> &CORE_0_PIF_PMS_CONSTRAIN_6

0x13c - Core0 access peripherals permission configuration register 6.

Source

pub fn core_0_pif_pms_constrain_7(&self) -> &CORE_0_PIF_PMS_CONSTRAIN_7

0x140 - Core0 access peripherals permission configuration register 7.

Source

pub fn core_0_pif_pms_constrain_8(&self) -> &CORE_0_PIF_PMS_CONSTRAIN_8

0x144 - Core0 access peripherals permission configuration register 8.

Source

pub fn core_0_pif_pms_constrain_9(&self) -> &CORE_0_PIF_PMS_CONSTRAIN_9

0x148 - Core0 access peripherals permission configuration register 9.

Source

pub fn core_0_pif_pms_constrain_10(&self) -> &CORE_0_PIF_PMS_CONSTRAIN_10

0x14c - Core0 access peripherals permission configuration register 10.

Source

pub fn core_0_pif_pms_constrain_11(&self) -> &CORE_0_PIF_PMS_CONSTRAIN_11

0x150 - Core0 access peripherals permission configuration register 11.

Source

pub fn core_0_pif_pms_constrain_12(&self) -> &CORE_0_PIF_PMS_CONSTRAIN_12

0x154 - Core0 access peripherals permission configuration register 12.

Source

pub fn core_0_pif_pms_constrain_13(&self) -> &CORE_0_PIF_PMS_CONSTRAIN_13

0x158 - Core0 access peripherals permission configuration register 13.

Source

pub fn core_0_pif_pms_constrain_14(&self) -> &CORE_0_PIF_PMS_CONSTRAIN_14

0x15c - Core0 access peripherals permission configuration register 14.

Source

pub fn core_0_region_pms_constrain_0(&self) -> &CORE_0_REGION_PMS_CONSTRAIN_0

0x160 - Core0 region permission register 0.

Source

pub fn core_0_region_pms_constrain_1(&self) -> &CORE_0_REGION_PMS_CONSTRAIN_1

0x164 - Core0 region permission register 1.

Source

pub fn core_0_region_pms_constrain_2(&self) -> &CORE_0_REGION_PMS_CONSTRAIN_2

0x168 - Core0 region permission register 2.

Source

pub fn core_0_region_pms_constrain_3(&self) -> &CORE_0_REGION_PMS_CONSTRAIN_3

0x16c - Core0 region permission register 3.

Source

pub fn core_0_region_pms_constrain_4(&self) -> &CORE_0_REGION_PMS_CONSTRAIN_4

0x170 - Core0 region permission register 4.

Source

pub fn core_0_region_pms_constrain_5(&self) -> &CORE_0_REGION_PMS_CONSTRAIN_5

0x174 - Core0 region permission register 5.

Source

pub fn core_0_region_pms_constrain_6(&self) -> &CORE_0_REGION_PMS_CONSTRAIN_6

0x178 - Core0 region permission register 6.

Source

pub fn core_0_region_pms_constrain_7(&self) -> &CORE_0_REGION_PMS_CONSTRAIN_7

0x17c - Core0 region permission register 7.

Source

pub fn core_0_region_pms_constrain_8(&self) -> &CORE_0_REGION_PMS_CONSTRAIN_8

0x180 - Core0 region permission register 8.

Source

pub fn core_0_region_pms_constrain_9(&self) -> &CORE_0_REGION_PMS_CONSTRAIN_9

0x184 - Core0 region permission register 9.

Source

pub fn core_0_region_pms_constrain_10(&self) -> &CORE_0_REGION_PMS_CONSTRAIN_10

0x188 - Core0 region permission register 10.

Source

pub fn core_0_region_pms_constrain_11(&self) -> &CORE_0_REGION_PMS_CONSTRAIN_11

0x18c - Core0 region permission register 11.

Source

pub fn core_0_region_pms_constrain_12(&self) -> &CORE_0_REGION_PMS_CONSTRAIN_12

0x190 - Core0 region permission register 12.

Source

pub fn core_0_region_pms_constrain_13(&self) -> &CORE_0_REGION_PMS_CONSTRAIN_13

0x194 - Core0 region permission register 13.

Source

pub fn core_0_region_pms_constrain_14(&self) -> &CORE_0_REGION_PMS_CONSTRAIN_14

0x198 - Core0 region permission register 14.

Source

pub fn core_0_pif_pms_monitor_0(&self) -> &CORE_0_PIF_PMS_MONITOR_0

0x19c - Core0 permission report register 0.

Source

pub fn core_0_pif_pms_monitor_1(&self) -> &CORE_0_PIF_PMS_MONITOR_1

0x1a0 - Core0 permission report register 1.

Source

pub fn core_0_pif_pms_monitor_2(&self) -> &CORE_0_PIF_PMS_MONITOR_2

0x1a4 - Core0 permission report register 2.

Source

pub fn core_0_pif_pms_monitor_3(&self) -> &CORE_0_PIF_PMS_MONITOR_3

0x1a8 - Core0 permission report register 3.

Source

pub fn core_0_pif_pms_monitor_4(&self) -> &CORE_0_PIF_PMS_MONITOR_4

0x1ac - Core0 permission report register 4.

Source

pub fn core_0_pif_pms_monitor_5(&self) -> &CORE_0_PIF_PMS_MONITOR_5

0x1b0 - Core0 permission report register 5.

Source

pub fn core_0_pif_pms_monitor_6(&self) -> &CORE_0_PIF_PMS_MONITOR_6

0x1b4 - Core0 permission report register 6.

Source

pub fn core_0_vecbase_override_lock(&self) -> &CORE_0_VECBASE_OVERRIDE_LOCK

0x1b8 - core0 vecbase override configuration register 0

Source

pub fn core_0_vecbase_override_0(&self) -> &CORE_0_VECBASE_OVERRIDE_0

0x1bc - core0 vecbase override configuration register 0

Source

pub fn core_0_vecbase_override_1(&self) -> &CORE_0_VECBASE_OVERRIDE_1

0x1c0 - core0 vecbase override configuration register 1

Source

pub fn core_0_vecbase_override_2(&self) -> &CORE_0_VECBASE_OVERRIDE_2

0x1c4 - core0 vecbase override configuration register 1

Source

pub fn core_0_toomanyexceptions_m_override_0( &self, ) -> &CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0

0x1c8 - core0 toomanyexception override configuration register 0.

Source

pub fn core_0_toomanyexceptions_m_override_1( &self, ) -> &CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1

0x1cc - core0 toomanyexception override configuration register 1.

Source

pub fn core_1_pif_pms_constrain_0(&self) -> &CORE_1_PIF_PMS_CONSTRAIN_0

0x1d0 - Core1 access peripherals permission configuration register 0.

Source

pub fn core_1_pif_pms_constrain_1(&self) -> &CORE_1_PIF_PMS_CONSTRAIN_1

0x1d4 - Core1 access peripherals permission configuration register 1.

Source

pub fn core_1_pif_pms_constrain_2(&self) -> &CORE_1_PIF_PMS_CONSTRAIN_2

0x1d8 - Core1 access peripherals permission configuration register 2.

Source

pub fn core_1_pif_pms_constrain_3(&self) -> &CORE_1_PIF_PMS_CONSTRAIN_3

0x1dc - Core1 access peripherals permission configuration register 3.

Source

pub fn core_1_pif_pms_constrain_4(&self) -> &CORE_1_PIF_PMS_CONSTRAIN_4

0x1e0 - Core1 access peripherals permission configuration register 4.

Source

pub fn core_1_pif_pms_constrain_5(&self) -> &CORE_1_PIF_PMS_CONSTRAIN_5

0x1e4 - Core1 access peripherals permission configuration register 5.

Source

pub fn core_1_pif_pms_constrain_6(&self) -> &CORE_1_PIF_PMS_CONSTRAIN_6

0x1e8 - Core1 access peripherals permission configuration register 6.

Source

pub fn core_1_pif_pms_constrain_7(&self) -> &CORE_1_PIF_PMS_CONSTRAIN_7

0x1ec - Core1 access peripherals permission configuration register 7.

Source

pub fn core_1_pif_pms_constrain_8(&self) -> &CORE_1_PIF_PMS_CONSTRAIN_8

0x1f0 - Core1 access peripherals permission configuration register 8.

Source

pub fn core_1_pif_pms_constrain_9(&self) -> &CORE_1_PIF_PMS_CONSTRAIN_9

0x1f4 - Core1 access peripherals permission configuration register 9.

Source

pub fn core_1_pif_pms_constrain_10(&self) -> &CORE_1_PIF_PMS_CONSTRAIN_10

0x1f8 - core1 access peripherals permission configuration register 10.

Source

pub fn core_1_pif_pms_constrain_11(&self) -> &CORE_1_PIF_PMS_CONSTRAIN_11

0x1fc - core1 access peripherals permission configuration register 11.

Source

pub fn core_1_pif_pms_constrain_12(&self) -> &CORE_1_PIF_PMS_CONSTRAIN_12

0x200 - core1 access peripherals permission configuration register 12.

Source

pub fn core_1_pif_pms_constrain_13(&self) -> &CORE_1_PIF_PMS_CONSTRAIN_13

0x204 - core1 access peripherals permission configuration register 13.

Source

pub fn core_1_pif_pms_constrain_14(&self) -> &CORE_1_PIF_PMS_CONSTRAIN_14

0x208 - core1 access peripherals permission configuration register 14.

Source

pub fn core_1_region_pms_constrain_0(&self) -> &CORE_1_REGION_PMS_CONSTRAIN_0

0x20c - core1 region permission register 0.

Source

pub fn core_1_region_pms_constrain_1(&self) -> &CORE_1_REGION_PMS_CONSTRAIN_1

0x210 - core1 region permission register 1.

Source

pub fn core_1_region_pms_constrain_2(&self) -> &CORE_1_REGION_PMS_CONSTRAIN_2

0x214 - core1 region permission register 2.

Source

pub fn core_1_region_pms_constrain_3(&self) -> &CORE_1_REGION_PMS_CONSTRAIN_3

0x218 - core1 region permission register 3.

Source

pub fn core_1_region_pms_constrain_4(&self) -> &CORE_1_REGION_PMS_CONSTRAIN_4

0x21c - core1 region permission register 4.

Source

pub fn core_1_region_pms_constrain_5(&self) -> &CORE_1_REGION_PMS_CONSTRAIN_5

0x220 - core1 region permission register 5.

Source

pub fn core_1_region_pms_constrain_6(&self) -> &CORE_1_REGION_PMS_CONSTRAIN_6

0x224 - core1 region permission register 6.

Source

pub fn core_1_region_pms_constrain_7(&self) -> &CORE_1_REGION_PMS_CONSTRAIN_7

0x228 - core1 region permission register 7.

Source

pub fn core_1_region_pms_constrain_8(&self) -> &CORE_1_REGION_PMS_CONSTRAIN_8

0x22c - core1 region permission register 8.

Source

pub fn core_1_region_pms_constrain_9(&self) -> &CORE_1_REGION_PMS_CONSTRAIN_9

0x230 - core1 region permission register 9.

Source

pub fn core_1_region_pms_constrain_10(&self) -> &CORE_1_REGION_PMS_CONSTRAIN_10

0x234 - core1 region permission register 10.

Source

pub fn core_1_region_pms_constrain_11(&self) -> &CORE_1_REGION_PMS_CONSTRAIN_11

0x238 - core1 region permission register 11.

Source

pub fn core_1_region_pms_constrain_12(&self) -> &CORE_1_REGION_PMS_CONSTRAIN_12

0x23c - core1 region permission register 12.

Source

pub fn core_1_region_pms_constrain_13(&self) -> &CORE_1_REGION_PMS_CONSTRAIN_13

0x240 - core1 region permission register 13.

Source

pub fn core_1_region_pms_constrain_14(&self) -> &CORE_1_REGION_PMS_CONSTRAIN_14

0x244 - core1 region permission register 14.

Source

pub fn core_1_pif_pms_monitor_0(&self) -> &CORE_1_PIF_PMS_MONITOR_0

0x248 - core1 permission report register 0.

Source

pub fn core_1_pif_pms_monitor_1(&self) -> &CORE_1_PIF_PMS_MONITOR_1

0x24c - core1 permission report register 1.

Source

pub fn core_1_pif_pms_monitor_2(&self) -> &CORE_1_PIF_PMS_MONITOR_2

0x250 - core1 permission report register 2.

Source

pub fn core_1_pif_pms_monitor_3(&self) -> &CORE_1_PIF_PMS_MONITOR_3

0x254 - core1 permission report register 3.

Source

pub fn core_1_pif_pms_monitor_4(&self) -> &CORE_1_PIF_PMS_MONITOR_4

0x258 - core1 permission report register 4.

Source

pub fn core_1_pif_pms_monitor_5(&self) -> &CORE_1_PIF_PMS_MONITOR_5

0x25c - core1 permission report register 5.

Source

pub fn core_1_pif_pms_monitor_6(&self) -> &CORE_1_PIF_PMS_MONITOR_6

0x260 - core1 permission report register 6.

Source

pub fn core_1_vecbase_override_lock(&self) -> &CORE_1_VECBASE_OVERRIDE_LOCK

0x264 - core1 vecbase override configuration register 0

Source

pub fn core_1_vecbase_override_0(&self) -> &CORE_1_VECBASE_OVERRIDE_0

0x268 - core1 vecbase override configuration register 0

Source

pub fn core_1_vecbase_override_1(&self) -> &CORE_1_VECBASE_OVERRIDE_1

0x26c - core1 vecbase override configuration register 1

Source

pub fn core_1_vecbase_override_2(&self) -> &CORE_1_VECBASE_OVERRIDE_2

0x270 - core1 vecbase override configuration register 1

Source

pub fn core_1_toomanyexceptions_m_override_0( &self, ) -> &CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0

0x274 - core1 toomanyexception override configuration register 0.

Source

pub fn core_1_toomanyexceptions_m_override_1( &self, ) -> &CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1

0x278 - core1 toomanyexception override configuration register 1.

Source

pub fn backup_bus_pms_constrain_0(&self) -> &BACKUP_BUS_PMS_CONSTRAIN_0

0x27c - BackUp access peripherals permission configuration register 0.

Source

pub fn backup_bus_pms_constrain_1(&self) -> &BACKUP_BUS_PMS_CONSTRAIN_1

0x280 - BackUp access peripherals permission configuration register 1.

Source

pub fn backup_bus_pms_constrain_2(&self) -> &BACKUP_BUS_PMS_CONSTRAIN_2

0x284 - BackUp access peripherals permission configuration register 2.

Source

pub fn backup_bus_pms_constrain_3(&self) -> &BACKUP_BUS_PMS_CONSTRAIN_3

0x288 - BackUp access peripherals permission configuration register 3.

Source

pub fn backup_bus_pms_constrain_4(&self) -> &BACKUP_BUS_PMS_CONSTRAIN_4

0x28c - BackUp access peripherals permission configuration register 4.

Source

pub fn backup_bus_pms_constrain_5(&self) -> &BACKUP_BUS_PMS_CONSTRAIN_5

0x290 - BackUp access peripherals permission configuration register 5.

Source

pub fn backup_bus_pms_constrain_6(&self) -> &BACKUP_BUS_PMS_CONSTRAIN_6

0x294 - BackUp access peripherals permission configuration register 6.

Source

pub fn backup_bus_pms_monitor_0(&self) -> &BACKUP_BUS_PMS_MONITOR_0

0x298 - BackUp permission report register 0.

Source

pub fn backup_bus_pms_monitor_1(&self) -> &BACKUP_BUS_PMS_MONITOR_1

0x29c - BackUp permission report register 1.

Source

pub fn backup_bus_pms_monitor_2(&self) -> &BACKUP_BUS_PMS_MONITOR_2

0x2a0 - BackUp permission report register 2.

Source

pub fn backup_bus_pms_monitor_3(&self) -> &BACKUP_BUS_PMS_MONITOR_3

0x2a4 - BackUp permission report register 3.

Source

pub fn edma_boundary_lock(&self) -> &EDMA_BOUNDARY_LOCK

0x2a8 - EDMA boundary lock register.

Source

pub fn edma_boundary_0(&self) -> &EDMA_BOUNDARY_0

0x2ac - EDMA boundary 0 configuration

Source

pub fn edma_boundary_1(&self) -> &EDMA_BOUNDARY_1

0x2b0 - EDMA boundary 1 configuration

Source

pub fn edma_boundary_2(&self) -> &EDMA_BOUNDARY_2

0x2b4 - EDMA boundary 2 configuration

Source

pub fn edma_pms_spi2_lock(&self) -> &EDMA_PMS_SPI2_LOCK

0x2b8 - EDMA-SPI2 permission lock register.

Source

pub fn edma_pms_spi2(&self) -> &EDMA_PMS_SPI2

0x2bc - EDMA-SPI2 permission control register.

Source

pub fn edma_pms_spi3_lock(&self) -> &EDMA_PMS_SPI3_LOCK

0x2c0 - EDMA-SPI3 permission lock register.

Source

pub fn edma_pms_spi3(&self) -> &EDMA_PMS_SPI3

0x2c4 - EDMA-SPI3 permission control register.

Source

pub fn edma_pms_uhci0_lock(&self) -> &EDMA_PMS_UHCI0_LOCK

0x2c8 - EDMA-UHCI0 permission lock register.

Source

pub fn edma_pms_uhci0(&self) -> &EDMA_PMS_UHCI0

0x2cc - EDMA-UHCI0 permission control register.

Source

pub fn edma_pms_i2s0_lock(&self) -> &EDMA_PMS_I2S0_LOCK

0x2d0 - EDMA-I2S0 permission lock register.

Source

pub fn edma_pms_i2s0(&self) -> &EDMA_PMS_I2S0

0x2d4 - EDMA-I2S0 permission control register.

Source

pub fn edma_pms_i2s1_lock(&self) -> &EDMA_PMS_I2S1_LOCK

0x2d8 - EDMA-I2S1 permission lock register.

Source

pub fn edma_pms_i2s1(&self) -> &EDMA_PMS_I2S1

0x2dc - EDMA-I2S1 permission control register.

Source

pub fn edma_pms_lcd_cam_lock(&self) -> &EDMA_PMS_LCD_CAM_LOCK

0x2e0 - EDMA-LCD/CAM permission lock register.

Source

pub fn edma_pms_lcd_cam(&self) -> &EDMA_PMS_LCD_CAM

0x2e4 - EDMA-LCD/CAM permission control register.

Source

pub fn edma_pms_aes_lock(&self) -> &EDMA_PMS_AES_LOCK

0x2e8 - EDMA-AES permission lock register.

Source

pub fn edma_pms_aes(&self) -> &EDMA_PMS_AES

0x2ec - EDMA-AES permission control register.

Source

pub fn edma_pms_sha_lock(&self) -> &EDMA_PMS_SHA_LOCK

0x2f0 - EDMA-SHA permission lock register.

Source

pub fn edma_pms_sha(&self) -> &EDMA_PMS_SHA

0x2f4 - EDMA-SHA permission control register.

Source

pub fn edma_pms_adc_dac_lock(&self) -> &EDMA_PMS_ADC_DAC_LOCK

0x2f8 - EDMA-ADC/DAC permission lock register.

Source

pub fn edma_pms_adc_dac(&self) -> &EDMA_PMS_ADC_DAC

0x2fc - EDMA-ADC/DAC permission control register.

Source

pub fn edma_pms_rmt_lock(&self) -> &EDMA_PMS_RMT_LOCK

0x300 - EDMA-RMT permission lock register.

Source

pub fn edma_pms_rmt(&self) -> &EDMA_PMS_RMT

0x304 - EDMA-RMT permission control register.

Source

pub fn clock_gate(&self) -> &CLOCK_GATE

0x308 - Sensitive module clock gate configuration register.

Source

pub fn rtc_pms(&self) -> &RTC_PMS

0x30c - RTC coprocessor permission register.

Source

pub fn date(&self) -> &DATE

0xffc - Sensitive version register.

Trait Implementations§

Source§

impl Debug for SENSITIVE

Source§

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more
Source§

impl Deref for SENSITIVE

Source§

type Target = RegisterBlock

The resulting type after dereferencing.
Source§

fn deref(&self) -> &Self::Target

Dereferences the value.
Source§

impl Send for SENSITIVE

Auto Trait Implementations§

Blanket Implementations§

Source§

impl<T> Any for T
where T: 'static + ?Sized,

Source§

fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more
Source§

impl<T> Borrow<T> for T
where T: ?Sized,

Source§

fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more
Source§

impl<T> BorrowMut<T> for T
where T: ?Sized,

Source§

fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more
Source§

impl<T> From<T> for T

Source§

fn from(t: T) -> T

Returns the argument unchanged.

Source§

impl<T, U> Into<U> for T
where U: From<T>,

Source§

fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

Source§

impl<P, T> Receiver for P
where P: Deref<Target = T> + ?Sized, T: ?Sized,

Source§

type Target = T

🔬This is a nightly-only experimental API. (arbitrary_self_types)
The target type on which the method may be called.
Source§

impl<T, U> TryFrom<U> for T
where U: Into<T>,

Source§

type Error = Infallible

The type returned in the event of a conversion error.
Source§

fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

Performs the conversion.
Source§

impl<T, U> TryInto<U> for T
where U: TryFrom<T>,

Source§

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.
Source§

fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.