Struct SPI0

pub struct SPI0 { /* private fields */ }

SPI (Serial Peripheral Interface) Controller 0

Implementations

impl SPI0

pub const PTR: *const RegisterBlock = {0x60003000 as *const spi0::RegisterBlock}

Pointer to the register block

pub const fn ptr() -> *const RegisterBlock

Return the pointer to the register block

pub unsafe fn steal() -> Self

Steal an instance of this peripheral

Safety

Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.

Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.

Methods from Deref<Target = RegisterBlock>

pub fn ctrl(&self) -> &CTRL

0x08 - SPI0 control register.

pub fn ctrl1(&self) -> &CTRL1

0x0c - SPI0 control 1 register.

pub fn ctrl2(&self) -> &CTRL2

0x10 - SPI0 control 2 register.

pub fn clock(&self) -> &CLOCK

0x14 - SPI_CLK clock division register when SPI0 accesses to flash.

pub fn user(&self) -> &USER

0x18 - SPI0 user register.

pub fn user1(&self) -> &USER1

0x1c - SPI0 user1 register.

pub fn user2(&self) -> &USER2

0x20 - SPI0 user2 register.

pub fn rd_status(&self) -> &RD_STATUS

0x2c - SPI0 read control register.

pub fn ext_addr(&self) -> &EXT_ADDR

0x30 - SPI0 extended address register.

pub fn misc(&self) -> &MISC

0x34 - SPI0 misc register

pub fn cache_fctrl(&self) -> &CACHE_FCTRL

0x3c - SPI0 external RAM bit mode control register.

pub fn cache_sctrl(&self) -> &CACHE_SCTRL

0x40 - SPI0 external RAM control register

pub fn sram_cmd(&self) -> &SRAM_CMD

0x44 - SPI0 external RAM mode control register

pub fn sram_drd_cmd(&self) -> &SRAM_DRD_CMD

0x48 - SPI0 external RAM DDR read command control register

pub fn sram_dwr_cmd(&self) -> &SRAM_DWR_CMD

0x4c - SPI0 external RAM DDR write command control register

pub fn sram_clk(&self) -> &SRAM_CLK

0x50 - SPI_CLK clock division register when SPI0 accesses to Ext_RAM.

pub fn fsm(&self) -> &FSM

0x54 - SPI0 state machine(FSM) status register.

pub fn timing_cali(&self) -> &TIMING_CALI

0xa8 - SPI0 timing compensation register when accesses to flash.

pub fn din_mode(&self) -> &DIN_MODE

0xac - MSPI input timing delay mode control register when accesses to flash.

pub fn din_num(&self) -> &DIN_NUM

0xb0 - MSPI input timing delay number control register when accesses to flash.

pub fn dout_mode(&self) -> &DOUT_MODE

0xb4 - MSPI output timing delay mode control register when accesses to flash.

pub fn spi_smem_timing_cali(&self) -> &SPI_SMEM_TIMING_CALI

0xbc - SPI0 Ext_RAM timing compensation register.

pub fn spi_smem_din_mode(&self) -> &SPI_SMEM_DIN_MODE

0xc0 - MSPI input timing delay mode control register when accesses to Ext_RAM.

pub fn spi_smem_din_num(&self) -> &SPI_SMEM_DIN_NUM

0xc4 - MSPI input timing delay number control register when accesses to Ext_RAM.

pub fn spi_smem_dout_mode(&self) -> &SPI_SMEM_DOUT_MODE

0xc8 - MSPI output timing delay mode control register when accesses to Ext_RAM.

pub fn ecc_ctrl(&self) -> &ECC_CTRL

0xcc - MSPI ECC control register

pub fn ecc_err_addr(&self) -> &ECC_ERR_ADDR

0xd0 - MSPI ECC error address register

pub fn ecc_err_bit(&self) -> &ECC_ERR_BIT

0xd4 - MSPI ECC error bits register

pub fn spi_smem_ac(&self) -> &SPI_SMEM_AC

0xdc - MSPI external RAM ECC and SPI CS timing control register

pub fn ddr(&self) -> &DDR

0xe0 - SPI0 flash DDR mode control register

pub fn spi_smem_ddr(&self) -> &SPI_SMEM_DDR

0xe4 - SPI0 external RAM DDR mode control register

pub fn clock_gate(&self) -> &CLOCK_GATE

0xe8 - SPI0 clk_gate register

pub fn core_clk_sel(&self) -> &CORE_CLK_SEL

0xec - SPI0 module clock select register

pub fn int_ena(&self) -> &INT_ENA

0xf0 - SPI1 interrupt enable register

pub fn int_clr(&self) -> &INT_CLR

0xf4 - SPI1 interrupt clear register

pub fn int_raw(&self) -> &INT_RAW

0xf8 - SPI1 interrupt raw register

pub fn int_st(&self) -> &INT_ST

0xfc - SPI1 interrupt status register

pub fn date(&self) -> &DATE

0x3fc - SPI0 version control register

Trait Implementations

impl Debug for SPI0

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Deref for SPI0

type Target = RegisterBlock

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl Send for SPI0