Struct esp32s3::extmem::core1_acs_cache_int_st::R

pub struct R(_);

Register CORE1_ACS_CACHE_INT_ST reader

Implementations

impl R

pub fn core1_ibus_acs_msk_icache_st(&self) -> CORE1_IBUS_ACS_MSK_ICACHE_ST_R

Bit 0 - The bit is used to indicate interrupt by cpu access icache while the core1_ibus is disabled or icache is disabled which include speculative access.

pub fn core1_ibus_wr_icache_st(&self) -> CORE1_IBUS_WR_ICACHE_ST_R

Bit 1 - The bit is used to indicate interrupt by ibus trying to write icache

pub fn core1_ibus_reject_st(&self) -> CORE1_IBUS_REJECT_ST_R

Bit 2 - The bit is used to indicate interrupt by authentication fail.

pub fn core1_dbus_acs_msk_dcache_st(&self) -> CORE1_DBUS_ACS_MSK_DCACHE_ST_R

Bit 3 - The bit is used to indicate interrupt by cpu access dcache while the core1_dbus is disabled or dcache is disabled which include speculative access.

pub fn core1_dbus_reject_st(&self) -> CORE1_DBUS_REJECT_ST_R

Bit 4 - The bit is used to indicate interrupt by authentication fail.

Methods from Deref<Target = R<CORE1_ACS_CACHE_INT_ST_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CORE1_ACS_CACHE_INT_ST_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<CORE1_ACS_CACHE_INT_ST_SPEC>> for R

fn from(reader: R<CORE1_ACS_CACHE_INT_ST_SPEC>) -> Self

Converts to this type from the input type.