Struct esp32s3::usb_device::conf0::R

pub struct R(_);

Register CONF0 reader

Implementations

impl R

pub fn phy_sel(&self) -> PHY_SEL_R

Bit 0 - Select internal/external PHY

pub fn exchg_pins_override(&self) -> EXCHG_PINS_OVERRIDE_R

Bit 1 - Enable software control USB D+ D- exchange

pub fn exchg_pins(&self) -> EXCHG_PINS_R

Bit 2 - USB D+ D- exchange

pub fn vrefh(&self) -> VREFH_R

Bits 3:4 - Control single-end input high threshold,1.76V to 2V, step 80mV

pub fn vrefl(&self) -> VREFL_R

Bits 5:6 - Control single-end input low threshold,0.8V to 1.04V, step 80mV

pub fn vref_override(&self) -> VREF_OVERRIDE_R

Bit 7 - Enable software control input threshold

pub fn pad_pull_override(&self) -> PAD_PULL_OVERRIDE_R

Bit 8 - Enable software control USB D+ D- pullup pulldown

pub fn dp_pullup(&self) -> DP_PULLUP_R

Bit 9 - Control USB D+ pull up.

pub fn dp_pulldown(&self) -> DP_PULLDOWN_R

Bit 10 - Control USB D+ pull down.

pub fn dm_pullup(&self) -> DM_PULLUP_R

Bit 11 - Control USB D- pull up.

pub fn dm_pulldown(&self) -> DM_PULLDOWN_R

Bit 12 - Control USB D- pull down.

pub fn pullup_value(&self) -> PULLUP_VALUE_R

Bit 13 - Control pull up value.

pub fn usb_pad_enable(&self) -> USB_PAD_ENABLE_R

Bit 14 - Enable USB pad function.

pub fn phy_tx_edge_sel(&self) -> PHY_TX_EDGE_SEL_R

Bit 15 - 0: TX output at clock negedge. 1: Tx output at clock posedge.

pub fn usb_jtag_bridge_en(&self) -> USB_JTAG_BRIDGE_EN_R

Bit 16 - Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix.

Methods from Deref<Target = R<CONF0_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CONF0_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<CONF0_SPEC>> for R

fn from(reader: R<CONF0_SPEC>) -> Self

Converts to this type from the input type.