Struct esp32s3::spi2::slave::W

pub struct W(_);

Register SLAVE writer

Implementations

impl W

pub fn clk_mode(&mut self) -> CLK_MODE_W<'_, 0>

Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.

pub fn clk_mode_13(&mut self) -> CLK_MODE_13_W<'_, 2>

Bit 2 - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].

pub fn rsck_data_out(&mut self) -> RSCK_DATA_OUT_W<'_, 3>

Bit 3 - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge

pub fn slv_rddma_bitlen_en(&mut self) -> SLV_RDDMA_BITLEN_EN_W<'_, 8>

Bit 8 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others

pub fn slv_wrdma_bitlen_en(&mut self) -> SLV_WRDMA_BITLEN_EN_W<'_, 9>

Bit 9 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others

pub fn slv_rdbuf_bitlen_en(&mut self) -> SLV_RDBUF_BITLEN_EN_W<'_, 10>

Bit 10 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others

pub fn slv_wrbuf_bitlen_en(&mut self) -> SLV_WRBUF_BITLEN_EN_W<'_, 11>

Bit 11 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others

pub fn dma_seg_magic_value(&mut self) -> DMA_SEG_MAGIC_VALUE_W<'_, 22>

Bits 22:25 - The magic value of BM table in master DMA seg-trans.

pub fn mode(&mut self) -> MODE_W<'_, 26>

Bit 26 - Set SPI work mode. 1: slave mode 0: master mode.

pub fn soft_reset(&mut self) -> SOFT_RESET_W<'_, 27>

Bit 27 - Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.

pub fn usr_conf(&mut self) -> USR_CONF_W<'_, 28>

Bit 28 - 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<SLAVE_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<SLAVE_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<SLAVE_SPEC>> for W

fn from(writer: W<SLAVE_SPEC>) -> Self

Converts to this type from the input type.