Struct esp32s3::spi0::ctrl2::W

source ·
pub struct W(_);
Expand description

Register CTRL2 writer

Implementations

Bits 0:4 - (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit.

Bits 5:9 - SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit.

Bits 10:12 - SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI_CS hold cycle in ECC mode when accessed flash.

Bit 13 - 1: MSPI skips page corner when accesses flash. 0: Not skip page corner when accesses flash.

Bit 14 - Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses flash.

Bits 25:30 - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.

Bit 31 - The FSM will be reset.

Writes raw bits to the register.

Methods from Deref<Target = W<CTRL2_SPEC>>

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

The resulting type after dereferencing.
Dereferences the value.
Mutably dereferences the value.
Converts to this type from the input type.

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Calls U::from(self).

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The type returned in the event of a conversion error.
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The type returned in the event of a conversion error.
Performs the conversion.