Struct esp32s3::spi0::cache_sctrl::R

source ·
pub struct R(_);
Expand description

Register CACHE_SCTRL reader

Implementations

Bit 0 - Set this bit to enable SPI0 read Ext_RAM with 32 bits address. The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31.

Bit 1 - Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM transfer.

Bit 2 - Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer.

Bit 3 - When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in write operations.

Bit 4 - When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in read operations.

Bit 5 - 1: The command value of SPI0 read Ext_RAM is SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE. 0: The value is 0x2.

Bits 6:11 - When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in read data transfer.

Bits 14:19 - When SPI0 accesses to Ext_RAM, it is the length in bits of ADDR phase. The register value shall be (bit_num-1).

Bit 20 - 1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE. 0: The value is 0x3.

Bit 21 - Set the bit to enable OPI mode in all SPI0 Ext_RAM transfer.

Bits 22:27 - When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in write data transfer.

Methods from Deref<Target = R<CACHE_SCTRL_SPEC>>

Reads raw bits from register.

Trait Implementations

The resulting type after dereferencing.
Dereferences the value.
Converts to this type from the input type.

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The type returned in the event of a conversion error.
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