Struct esp32s3::spi0::cache_sctrl::R
source · pub struct R(_);
Expand description
Register CACHE_SCTRL
reader
Implementations
sourceimpl R
impl R
sourcepub fn cache_usr_scmd_4byte(&self) -> CACHE_USR_SCMD_4BYTE_R
pub fn cache_usr_scmd_4byte(&self) -> CACHE_USR_SCMD_4BYTE_R
Bit 0 - Set this bit to enable SPI0 read Ext_RAM with 32 bits address. The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31.
sourcepub fn usr_sram_dio(&self) -> USR_SRAM_DIO_R
pub fn usr_sram_dio(&self) -> USR_SRAM_DIO_R
Bit 1 - Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM transfer.
sourcepub fn usr_sram_qio(&self) -> USR_SRAM_QIO_R
pub fn usr_sram_qio(&self) -> USR_SRAM_QIO_R
Bit 2 - Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer.
sourcepub fn usr_wr_sram_dummy(&self) -> USR_WR_SRAM_DUMMY_R
pub fn usr_wr_sram_dummy(&self) -> USR_WR_SRAM_DUMMY_R
Bit 3 - When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in write operations.
sourcepub fn usr_rd_sram_dummy(&self) -> USR_RD_SRAM_DUMMY_R
pub fn usr_rd_sram_dummy(&self) -> USR_RD_SRAM_DUMMY_R
Bit 4 - When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in read operations.
sourcepub fn cache_sram_usr_rcmd(&self) -> CACHE_SRAM_USR_RCMD_R
pub fn cache_sram_usr_rcmd(&self) -> CACHE_SRAM_USR_RCMD_R
Bit 5 - 1: The command value of SPI0 read Ext_RAM is SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE. 0: The value is 0x2.
sourcepub fn sram_rdummy_cyclelen(&self) -> SRAM_RDUMMY_CYCLELEN_R
pub fn sram_rdummy_cyclelen(&self) -> SRAM_RDUMMY_CYCLELEN_R
Bits 6:11 - When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in read data transfer.
sourcepub fn sram_addr_bitlen(&self) -> SRAM_ADDR_BITLEN_R
pub fn sram_addr_bitlen(&self) -> SRAM_ADDR_BITLEN_R
Bits 14:19 - When SPI0 accesses to Ext_RAM, it is the length in bits of ADDR phase. The register value shall be (bit_num-1).
sourcepub fn cache_sram_usr_wcmd(&self) -> CACHE_SRAM_USR_WCMD_R
pub fn cache_sram_usr_wcmd(&self) -> CACHE_SRAM_USR_WCMD_R
Bit 20 - 1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE. 0: The value is 0x3.
sourcepub fn sram_oct(&self) -> SRAM_OCT_R
pub fn sram_oct(&self) -> SRAM_OCT_R
Bit 21 - Set the bit to enable OPI mode in all SPI0 Ext_RAM transfer.
sourcepub fn sram_wdummy_cyclelen(&self) -> SRAM_WDUMMY_CYCLELEN_R
pub fn sram_wdummy_cyclelen(&self) -> SRAM_WDUMMY_CYCLELEN_R
Bits 22:27 - When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in write data transfer.