Struct esp32s3::dma::in_int_raw_ch::R

pub struct R(_);

Register IN_INT_RAW_CH%s reader

Implementations

impl R

pub fn in_done(&self) -> IN_DONE_R

Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.

pub fn in_suc_eof(&self) -> IN_SUC_EOF_R

Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.

pub fn in_err_eof(&self) -> IN_ERR_EOF_R

Bit 2 - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved.

pub fn in_dscr_err(&self) -> IN_DSCR_ERR_R

Bit 3 - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0.

pub fn in_dscr_empty(&self) -> IN_DSCR_EMPTY_R

Bit 4 - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0.

pub fn infifo_full_wm(&self) -> INFIFO_FULL_WM_R

Bit 5 - The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0.

pub fn infifo_ovf_l1(&self) -> INFIFO_OVF_L1_R

Bit 6 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow.

pub fn infifo_udf_l1(&self) -> INFIFO_UDF_L1_R

Bit 7 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow.

pub fn infifo_ovf_l3(&self) -> INFIFO_OVF_L3_R

Bit 8 - This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is overflow.

pub fn infifo_udf_l3(&self) -> INFIFO_UDF_L3_R

Bit 9 - This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is underflow.

Methods from Deref<Target = R<IN_INT_RAW_CH_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<IN_INT_RAW_CH_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<IN_INT_RAW_CH_SPEC>> for R

fn from(reader: R<IN_INT_RAW_CH_SPEC>) -> Self

Converts to this type from the input type.