Struct esp32s3::uhci0::int_st::R

pub struct R(_);

Register INT_ST reader

Implementations

impl R

pub fn rx_start_int_st(&self) -> RX_START_INT_ST_R

Bit 0 - This is the masked interrupt bit for UHCI_RX_START_INT interrupt when UHCI_RX_START_INT_ENA is set to 1.

pub fn tx_start_int_st(&self) -> TX_START_INT_ST_R

Bit 1 - This is the masked interrupt bit for UHCI_TX_START_INT interrupt when UHCI_TX_START_INT_ENA is set to 1.

pub fn rx_hung_int_st(&self) -> RX_HUNG_INT_ST_R

Bit 2 - This is the masked interrupt bit for UHCI_RX_HUNG_INT interrupt when UHCI_RX_HUNG_INT_ENA is set to 1.

pub fn tx_hung_int_st(&self) -> TX_HUNG_INT_ST_R

Bit 3 - This is the masked interrupt bit for UHCI_TX_HUNG_INT interrupt when UHCI_TX_HUNG_INT_ENA is set to 1.

pub fn send_s_reg_q_int_st(&self) -> SEND_S_REG_Q_INT_ST_R

Bit 4 - This is the masked interrupt bit for UHCI_SEND_S_REQ_Q_INT interrupt when UHCI_SEND_S_REQ_Q_INT_ENA is set to 1.

pub fn send_a_reg_q_int_st(&self) -> SEND_A_REG_Q_INT_ST_R

Bit 5 - This is the masked interrupt bit for UHCI_SEND_A_REQ_Q_INT interrupt when UHCI_SEND_A_REQ_Q_INT_ENA is set to 1.

pub fn outlink_eof_err_int_st(&self) -> OUTLINK_EOF_ERR_INT_ST_R

Bit 6 - This is the masked interrupt bit for UHCI_OUTLINK_EOF_ERR_INT interrupt when UHCI_OUTLINK_EOF_ERR_INT_ENA is set to 1.

pub fn app_ctrl0_int_st(&self) -> APP_CTRL0_INT_ST_R

Bit 7 - This is the masked interrupt bit for UHCI_APP_CTRL0_INT interrupt when UHCI_APP_CTRL0_INT_ENA is set to 1.

pub fn app_ctrl1_int_st(&self) -> APP_CTRL1_INT_ST_R

Bit 8 - This is the masked interrupt bit for UHCI_APP_CTRL1_INT interrupt when UHCI_APP_CTRL1_INT_ENA is set to 1.

Methods from Deref<Target = R<INT_ST_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<INT_ST_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<INT_ST_SPEC>> for R

fn from(reader: R<INT_ST_SPEC>) -> Self

Converts to this type from the input type.