Struct esp32s3::pwm0::int_st::R

pub struct R(_);

Register INT_ST reader

Implementations

impl R

pub fn timer0_stop_int_st(&self) -> TIMER0_STOP_INT_ST_R

Bit 0 - The masked status bit for the interrupt triggered when the timer 0 stops.

pub fn timer1_stop_int_st(&self) -> TIMER1_STOP_INT_ST_R

Bit 1 - The masked status bit for the interrupt triggered when the timer 1 stops.

pub fn timer2_stop_int_st(&self) -> TIMER2_STOP_INT_ST_R

Bit 2 - The masked status bit for the interrupt triggered when the timer 2 stops.

pub fn timer0_tez_int_st(&self) -> TIMER0_TEZ_INT_ST_R

Bit 3 - The masked status bit for the interrupt triggered by a PWM timer 0 TEZ event.

pub fn timer1_tez_int_st(&self) -> TIMER1_TEZ_INT_ST_R

Bit 4 - The masked status bit for the interrupt triggered by a PWM timer 1 TEZ event.

pub fn timer2_tez_int_st(&self) -> TIMER2_TEZ_INT_ST_R

Bit 5 - The masked status bit for the interrupt triggered by a PWM timer 2 TEZ event.

pub fn timer0_tep_int_st(&self) -> TIMER0_TEP_INT_ST_R

Bit 6 - The masked status bit for the interrupt triggered by a PWM timer 0 TEP event.

pub fn timer1_tep_int_st(&self) -> TIMER1_TEP_INT_ST_R

Bit 7 - The masked status bit for the interrupt triggered by a PWM timer 1 TEP event.

pub fn timer2_tep_int_st(&self) -> TIMER2_TEP_INT_ST_R

Bit 8 - The masked status bit for the interrupt triggered by a PWM timer 2 TEP event.

pub fn fault0_int_st(&self) -> FAULT0_INT_ST_R

Bit 9 - The masked status bit for the interrupt triggered when event_f0 starts.

pub fn fault1_int_st(&self) -> FAULT1_INT_ST_R

Bit 10 - The masked status bit for the interrupt triggered when event_f1 starts.

pub fn fault2_int_st(&self) -> FAULT2_INT_ST_R

Bit 11 - The masked status bit for the interrupt triggered when event_f2 starts.

pub fn fault0_clr_int_st(&self) -> FAULT0_CLR_INT_ST_R

Bit 12 - The masked status bit for the interrupt triggered when event_f0 ends.

pub fn fault1_clr_int_st(&self) -> FAULT1_CLR_INT_ST_R

Bit 13 - The masked status bit for the interrupt triggered when event_f1 ends.

pub fn fault2_clr_int_st(&self) -> FAULT2_CLR_INT_ST_R

Bit 14 - The masked status bit for the interrupt triggered when event_f2 ends.

pub fn cmpr0_tea_int_st(&self) -> CMPR0_TEA_INT_ST_R

Bit 15 - The masked status bit for the interrupt triggered by a PWM operator 0 TEA event

pub fn cmpr1_tea_int_st(&self) -> CMPR1_TEA_INT_ST_R

Bit 16 - The masked status bit for the interrupt triggered by a PWM operator 1 TEA event

pub fn cmpr2_tea_int_st(&self) -> CMPR2_TEA_INT_ST_R

Bit 17 - The masked status bit for the interrupt triggered by a PWM operator 2 TEA event

pub fn cmpr0_teb_int_st(&self) -> CMPR0_TEB_INT_ST_R

Bit 18 - The masked status bit for the interrupt triggered by a PWM operator 0 TEB event

pub fn cmpr1_teb_int_st(&self) -> CMPR1_TEB_INT_ST_R

Bit 19 - The masked status bit for the interrupt triggered by a PWM operator 1 TEB event

pub fn cmpr2_teb_int_st(&self) -> CMPR2_TEB_INT_ST_R

Bit 20 - The masked status bit for the interrupt triggered by a PWM operator 2 TEB event

pub fn tz0_cbc_int_st(&self) -> TZ0_CBC_INT_ST_R

Bit 21 - The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM0.

pub fn tz1_cbc_int_st(&self) -> TZ1_CBC_INT_ST_R

Bit 22 - The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM1.

pub fn tz2_cbc_int_st(&self) -> TZ2_CBC_INT_ST_R

Bit 23 - The masked status bit for the interrupt triggered by a cycle-by-cycle mode action on PWM2.

pub fn tz0_ost_int_st(&self) -> TZ0_OST_INT_ST_R

Bit 24 - The masked status bit for the interrupt triggered by a one-shot mode action on PWM0.

pub fn tz1_ost_int_st(&self) -> TZ1_OST_INT_ST_R

Bit 25 - The masked status bit for the interrupt triggered by a one-shot mode action on PWM1.

pub fn tz2_ost_int_st(&self) -> TZ2_OST_INT_ST_R

Bit 26 - The masked status bit for the interrupt triggered by a one-shot mode action on PWM2.

pub fn cap0_int_st(&self) -> CAP0_INT_ST_R

Bit 27 - The masked status bit for the interrupt triggered by capture on channel 0.

pub fn cap1_int_st(&self) -> CAP1_INT_ST_R

Bit 28 - The masked status bit for the interrupt triggered by capture on channel 1.

pub fn cap2_int_st(&self) -> CAP2_INT_ST_R

Bit 29 - The masked status bit for the interrupt triggered by capture on channel 2.

Methods from Deref<Target = R<INT_ST_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<INT_ST_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<INT_ST_SPEC>> for R

fn from(reader: R<INT_ST_SPEC>) -> Self

Converts to this type from the input type.