Module esp32s3::uhci0::int_st

Masked interrupt status

Structs

INT_ST_SPEC

Masked interrupt status

R

Register INT_ST reader

Type Definitions

APP_CTRL0_INT_ST_R

Field APP_CTRL0_INT_ST reader - This is the masked interrupt bit for UHCI_APP_CTRL0_INT interrupt when UHCI_APP_CTRL0_INT_ENA is set to 1.

APP_CTRL1_INT_ST_R

Field APP_CTRL1_INT_ST reader - This is the masked interrupt bit for UHCI_APP_CTRL1_INT interrupt when UHCI_APP_CTRL1_INT_ENA is set to 1.

OUTLINK_EOF_ERR_INT_ST_R

Field OUTLINK_EOF_ERR_INT_ST reader - This is the masked interrupt bit for UHCI_OUTLINK_EOF_ERR_INT interrupt when UHCI_OUTLINK_EOF_ERR_INT_ENA is set to 1.

RX_HUNG_INT_ST_R

Field RX_HUNG_INT_ST reader - This is the masked interrupt bit for UHCI_RX_HUNG_INT interrupt when UHCI_RX_HUNG_INT_ENA is set to 1.

RX_START_INT_ST_R

Field RX_START_INT_ST reader - This is the masked interrupt bit for UHCI_RX_START_INT interrupt when UHCI_RX_START_INT_ENA is set to 1.

SEND_A_REG_Q_INT_ST_R

Field SEND_A_REG_Q_INT_ST reader - This is the masked interrupt bit for UHCI_SEND_A_REQ_Q_INT interrupt when UHCI_SEND_A_REQ_Q_INT_ENA is set to 1.

SEND_S_REG_Q_INT_ST_R

Field SEND_S_REG_Q_INT_ST reader - This is the masked interrupt bit for UHCI_SEND_S_REQ_Q_INT interrupt when UHCI_SEND_S_REQ_Q_INT_ENA is set to 1.

TX_HUNG_INT_ST_R

Field TX_HUNG_INT_ST reader - This is the masked interrupt bit for UHCI_TX_HUNG_INT interrupt when UHCI_TX_HUNG_INT_ENA is set to 1.

TX_START_INT_ST_R

Field TX_START_INT_ST reader - This is the masked interrupt bit for UHCI_TX_START_INT interrupt when UHCI_TX_START_INT_ENA is set to 1.