pub struct W(_);Expand description
Register DIN_MODE writer
Implementations
sourceimpl W
impl W
sourcepub fn din0_mode(&mut self) -> DIN0_MODE_W<'_, 0>
pub fn din0_mode(&mut self) -> DIN0_MODE_W<'_, 0>
Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
sourcepub fn din1_mode(&mut self) -> DIN1_MODE_W<'_, 2>
pub fn din1_mode(&mut self) -> DIN1_MODE_W<'_, 2>
Bits 2:3 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
sourcepub fn din2_mode(&mut self) -> DIN2_MODE_W<'_, 4>
pub fn din2_mode(&mut self) -> DIN2_MODE_W<'_, 4>
Bits 4:5 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
sourcepub fn din3_mode(&mut self) -> DIN3_MODE_W<'_, 6>
pub fn din3_mode(&mut self) -> DIN3_MODE_W<'_, 6>
Bits 6:7 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
sourcepub fn din4_mode(&mut self) -> DIN4_MODE_W<'_, 8>
pub fn din4_mode(&mut self) -> DIN4_MODE_W<'_, 8>
Bits 8:9 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
sourcepub fn din5_mode(&mut self) -> DIN5_MODE_W<'_, 10>
pub fn din5_mode(&mut self) -> DIN5_MODE_W<'_, 10>
Bits 10:11 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
sourcepub fn din6_mode(&mut self) -> DIN6_MODE_W<'_, 12>
pub fn din6_mode(&mut self) -> DIN6_MODE_W<'_, 12>
Bits 12:13 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
sourcepub fn din7_mode(&mut self) -> DIN7_MODE_W<'_, 14>
pub fn din7_mode(&mut self) -> DIN7_MODE_W<'_, 14>
Bits 14:15 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
sourcepub fn timing_hclk_active(&mut self) -> TIMING_HCLK_ACTIVE_W<'_, 16>
pub fn timing_hclk_active(&mut self) -> TIMING_HCLK_ACTIVE_W<'_, 16>
Bit 16 - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state.