Struct esp32s3::ledc::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 54 fields
    pub ch0_conf0: CH_CONF0,
    pub ch0_hpoint: CH_HPOINT,
    pub ch0_duty: CH_DUTY,
    pub ch0_conf1: CH_CONF1,
    pub ch0_duty_r: CH_DUTY_R,
    pub ch1_conf0: CH_CONF0,
    pub ch1_hpoint: CH_HPOINT,
    pub ch1_duty: CH_DUTY,
    pub ch1_conf1: CH_CONF1,
    pub ch1_duty_r: CH_DUTY_R,
    pub ch2_conf0: CH_CONF0,
    pub ch2_hpoint: CH_HPOINT,
    pub ch2_duty: CH_DUTY,
    pub ch2_conf1: CH_CONF1,
    pub ch2_duty_r: CH_DUTY_R,
    pub ch3_conf0: CH_CONF0,
    pub ch3_hpoint: CH_HPOINT,
    pub ch3_duty: CH_DUTY,
    pub ch3_conf1: CH_CONF1,
    pub ch3_duty_r: CH_DUTY_R,
    pub ch4_conf0: CH_CONF0,
    pub ch4_hpoint: CH_HPOINT,
    pub ch4_duty: CH_DUTY,
    pub ch4_conf1: CH_CONF1,
    pub ch4_duty_r: CH_DUTY_R,
    pub ch5_conf0: CH_CONF0,
    pub ch5_hpoint: CH_HPOINT,
    pub ch5_duty: CH_DUTY,
    pub ch5_conf1: CH_CONF1,
    pub ch5_duty_r: CH_DUTY_R,
    pub ch6_conf0: CH_CONF0,
    pub ch6_hpoint: CH_HPOINT,
    pub ch6_duty: CH_DUTY,
    pub ch6_conf1: CH_CONF1,
    pub ch6_duty_r: CH_DUTY_R,
    pub ch7_conf0: CH_CONF0,
    pub ch7_hpoint: CH_HPOINT,
    pub ch7_duty: CH_DUTY,
    pub ch7_conf1: CH_CONF1,
    pub ch7_duty_r: CH_DUTY_R,
    pub timer0_conf: TIMER_CONF,
    pub timer0_value: TIMER_VALUE,
    pub timer1_conf: TIMER_CONF,
    pub timer1_value: TIMER_VALUE,
    pub timer2_conf: TIMER_CONF,
    pub timer2_value: TIMER_VALUE,
    pub timer3_conf: TIMER_CONF,
    pub timer3_value: TIMER_VALUE,
    pub int_raw: INT_RAW,
    pub int_st: INT_ST,
    pub int_ena: INT_ENA,
    pub int_clr: INT_CLR,
    pub conf: CONF,
    pub date: DATE,
    /* private fields */

}
Expand description

Register block

Fields

ch0_conf0: CH_CONF0

0x00 - Configuration register 0 for channel %s

ch0_hpoint: CH_HPOINT

0x04 - High point register for channel %s

ch0_duty: CH_DUTY

0x08 - Initial duty cycle for channel %s

ch0_conf1: CH_CONF1

0x0c - Configuration register 1 for channel %s

ch0_duty_r: CH_DUTY_R

0x10 - Current duty cycle for channel %s

ch1_conf0: CH_CONF0

0x14 - Configuration register 0 for channel %s

ch1_hpoint: CH_HPOINT

0x18 - High point register for channel %s

ch1_duty: CH_DUTY

0x1c - Initial duty cycle for channel %s

ch1_conf1: CH_CONF1

0x20 - Configuration register 1 for channel %s

ch1_duty_r: CH_DUTY_R

0x24 - Current duty cycle for channel %s

ch2_conf0: CH_CONF0

0x28 - Configuration register 0 for channel %s

ch2_hpoint: CH_HPOINT

0x2c - High point register for channel %s

ch2_duty: CH_DUTY

0x30 - Initial duty cycle for channel %s

ch2_conf1: CH_CONF1

0x34 - Configuration register 1 for channel %s

ch2_duty_r: CH_DUTY_R

0x38 - Current duty cycle for channel %s

ch3_conf0: CH_CONF0

0x3c - Configuration register 0 for channel %s

ch3_hpoint: CH_HPOINT

0x40 - High point register for channel %s

ch3_duty: CH_DUTY

0x44 - Initial duty cycle for channel %s

ch3_conf1: CH_CONF1

0x48 - Configuration register 1 for channel %s

ch3_duty_r: CH_DUTY_R

0x4c - Current duty cycle for channel %s

ch4_conf0: CH_CONF0

0x50 - Configuration register 0 for channel %s

ch4_hpoint: CH_HPOINT

0x54 - High point register for channel %s

ch4_duty: CH_DUTY

0x58 - Initial duty cycle for channel %s

ch4_conf1: CH_CONF1

0x5c - Configuration register 1 for channel %s

ch4_duty_r: CH_DUTY_R

0x60 - Current duty cycle for channel %s

ch5_conf0: CH_CONF0

0x64 - Configuration register 0 for channel %s

ch5_hpoint: CH_HPOINT

0x68 - High point register for channel %s

ch5_duty: CH_DUTY

0x6c - Initial duty cycle for channel %s

ch5_conf1: CH_CONF1

0x70 - Configuration register 1 for channel %s

ch5_duty_r: CH_DUTY_R

0x74 - Current duty cycle for channel %s

ch6_conf0: CH_CONF0

0x78 - Configuration register 0 for channel %s

ch6_hpoint: CH_HPOINT

0x7c - High point register for channel %s

ch6_duty: CH_DUTY

0x80 - Initial duty cycle for channel %s

ch6_conf1: CH_CONF1

0x84 - Configuration register 1 for channel %s

ch6_duty_r: CH_DUTY_R

0x88 - Current duty cycle for channel %s

ch7_conf0: CH_CONF0

0x8c - Configuration register 0 for channel %s

ch7_hpoint: CH_HPOINT

0x90 - High point register for channel %s

ch7_duty: CH_DUTY

0x94 - Initial duty cycle for channel %s

ch7_conf1: CH_CONF1

0x98 - Configuration register 1 for channel %s

ch7_duty_r: CH_DUTY_R

0x9c - Current duty cycle for channel %s

timer0_conf: TIMER_CONF

0xa0 - Timer %s configuration

timer0_value: TIMER_VALUE

0xa4 - Timer %s current counter value

timer1_conf: TIMER_CONF

0xa8 - Timer %s configuration

timer1_value: TIMER_VALUE

0xac - Timer %s current counter value

timer2_conf: TIMER_CONF

0xb0 - Timer %s configuration

timer2_value: TIMER_VALUE

0xb4 - Timer %s current counter value

timer3_conf: TIMER_CONF

0xb8 - Timer %s configuration

timer3_value: TIMER_VALUE

0xbc - Timer %s current counter value

int_raw: INT_RAW

0xc0 - Raw interrupt status

int_st: INT_ST

0xc4 - Masked interrupt status

int_ena: INT_ENA

0xc8 - Interrupt enable bits

int_clr: INT_CLR

0xcc - Interrupt clear bits

conf: CONF

0xd0 - Global ledc configuration register

date: DATE

0xfc - Version control register

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