Struct esp32s3::spi0::cache_sctrl::W
source · pub struct W(_);Expand description
Register CACHE_SCTRL writer
Implementations
sourceimpl W
impl W
sourcepub fn cache_usr_scmd_4byte(&mut self) -> CACHE_USR_SCMD_4BYTE_W<'_, 0>
pub fn cache_usr_scmd_4byte(&mut self) -> CACHE_USR_SCMD_4BYTE_W<'_, 0>
Bit 0 - Set this bit to enable SPI0 read Ext_RAM with 32 bits address. The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31.
sourcepub fn usr_sram_dio(&mut self) -> USR_SRAM_DIO_W<'_, 1>
pub fn usr_sram_dio(&mut self) -> USR_SRAM_DIO_W<'_, 1>
Bit 1 - Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM transfer.
sourcepub fn usr_sram_qio(&mut self) -> USR_SRAM_QIO_W<'_, 2>
pub fn usr_sram_qio(&mut self) -> USR_SRAM_QIO_W<'_, 2>
Bit 2 - Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer.
sourcepub fn usr_wr_sram_dummy(&mut self) -> USR_WR_SRAM_DUMMY_W<'_, 3>
pub fn usr_wr_sram_dummy(&mut self) -> USR_WR_SRAM_DUMMY_W<'_, 3>
Bit 3 - When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in write operations.
sourcepub fn usr_rd_sram_dummy(&mut self) -> USR_RD_SRAM_DUMMY_W<'_, 4>
pub fn usr_rd_sram_dummy(&mut self) -> USR_RD_SRAM_DUMMY_W<'_, 4>
Bit 4 - When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in read operations.
sourcepub fn cache_sram_usr_rcmd(&mut self) -> CACHE_SRAM_USR_RCMD_W<'_, 5>
pub fn cache_sram_usr_rcmd(&mut self) -> CACHE_SRAM_USR_RCMD_W<'_, 5>
Bit 5 - 1: The command value of SPI0 read Ext_RAM is SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE. 0: The value is 0x2.
sourcepub fn sram_rdummy_cyclelen(&mut self) -> SRAM_RDUMMY_CYCLELEN_W<'_, 6>
pub fn sram_rdummy_cyclelen(&mut self) -> SRAM_RDUMMY_CYCLELEN_W<'_, 6>
Bits 6:11 - When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in read data transfer.
sourcepub fn sram_addr_bitlen(&mut self) -> SRAM_ADDR_BITLEN_W<'_, 14>
pub fn sram_addr_bitlen(&mut self) -> SRAM_ADDR_BITLEN_W<'_, 14>
Bits 14:19 - When SPI0 accesses to Ext_RAM, it is the length in bits of ADDR phase. The register value shall be (bit_num-1).
sourcepub fn cache_sram_usr_wcmd(&mut self) -> CACHE_SRAM_USR_WCMD_W<'_, 20>
pub fn cache_sram_usr_wcmd(&mut self) -> CACHE_SRAM_USR_WCMD_W<'_, 20>
Bit 20 - 1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE. 0: The value is 0x3.
sourcepub fn sram_oct(&mut self) -> SRAM_OCT_W<'_, 21>
pub fn sram_oct(&mut self) -> SRAM_OCT_W<'_, 21>
Bit 21 - Set the bit to enable OPI mode in all SPI0 Ext_RAM transfer.
sourcepub fn sram_wdummy_cyclelen(&mut self) -> SRAM_WDUMMY_CYCLELEN_W<'_, 22>
pub fn sram_wdummy_cyclelen(&mut self) -> SRAM_WDUMMY_CYCLELEN_W<'_, 22>
Bits 22:27 - When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in write data transfer.