1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140

#[doc = "Register `APB_ADC_CLKM_CONF` reader"]
pub struct R(crate::R<APB_ADC_CLKM_CONF_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<APB_ADC_CLKM_CONF_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl From<crate::R<APB_ADC_CLKM_CONF_SPEC>> for R {
    #[inline(always)]
    fn from(reader: crate::R<APB_ADC_CLKM_CONF_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `APB_ADC_CLKM_CONF` writer"]
pub struct W(crate::W<APB_ADC_CLKM_CONF_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<APB_ADC_CLKM_CONF_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl From<crate::W<APB_ADC_CLKM_CONF_SPEC>> for W {
    #[inline(always)]
    fn from(writer: crate::W<APB_ADC_CLKM_CONF_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `CLKM_DIV_NUM` reader - Integral clock divider value"]
pub type CLKM_DIV_NUM_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CLKM_DIV_NUM` writer - Integral clock divider value"]
pub type CLKM_DIV_NUM_W<'a, const O: u8> =
    crate::FieldWriter<'a, u32, APB_ADC_CLKM_CONF_SPEC, u8, u8, 8, O>;
#[doc = "Field `CLKM_DIV_B` reader - Fractional clock divider numerator value"]
pub type CLKM_DIV_B_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CLKM_DIV_B` writer - Fractional clock divider numerator value"]
pub type CLKM_DIV_B_W<'a, const O: u8> =
    crate::FieldWriter<'a, u32, APB_ADC_CLKM_CONF_SPEC, u8, u8, 6, O>;
#[doc = "Field `CLKM_DIV_A` reader - Fractional clock divider denominator value"]
pub type CLKM_DIV_A_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CLKM_DIV_A` writer - Fractional clock divider denominator value"]
pub type CLKM_DIV_A_W<'a, const O: u8> =
    crate::FieldWriter<'a, u32, APB_ADC_CLKM_CONF_SPEC, u8, u8, 6, O>;
#[doc = "Field `CLK_EN` reader - no public"]
pub type CLK_EN_R = crate::BitReader<bool>;
#[doc = "Field `CLK_EN` writer - no public"]
pub type CLK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, APB_ADC_CLKM_CONF_SPEC, bool, O>;
#[doc = "Field `CLK_SEL` reader - Set this bit to enable clk_apll"]
pub type CLK_SEL_R = crate::FieldReader<u8, u8>;
#[doc = "Field `CLK_SEL` writer - Set this bit to enable clk_apll"]
pub type CLK_SEL_W<'a, const O: u8> =
    crate::FieldWriter<'a, u32, APB_ADC_CLKM_CONF_SPEC, u8, u8, 2, O>;
impl R {
    #[doc = "Bits 0:7 - Integral clock divider value"]
    #[inline(always)]
    pub fn clkm_div_num(&self) -> CLKM_DIV_NUM_R {
        CLKM_DIV_NUM_R::new((self.bits & 0xff) as u8)
    }
    #[doc = "Bits 8:13 - Fractional clock divider numerator value"]
    #[inline(always)]
    pub fn clkm_div_b(&self) -> CLKM_DIV_B_R {
        CLKM_DIV_B_R::new(((self.bits >> 8) & 0x3f) as u8)
    }
    #[doc = "Bits 14:19 - Fractional clock divider denominator value"]
    #[inline(always)]
    pub fn clkm_div_a(&self) -> CLKM_DIV_A_R {
        CLKM_DIV_A_R::new(((self.bits >> 14) & 0x3f) as u8)
    }
    #[doc = "Bit 20 - no public"]
    #[inline(always)]
    pub fn clk_en(&self) -> CLK_EN_R {
        CLK_EN_R::new(((self.bits >> 20) & 1) != 0)
    }
    #[doc = "Bits 21:22 - Set this bit to enable clk_apll"]
    #[inline(always)]
    pub fn clk_sel(&self) -> CLK_SEL_R {
        CLK_SEL_R::new(((self.bits >> 21) & 3) as u8)
    }
}
impl W {
    #[doc = "Bits 0:7 - Integral clock divider value"]
    #[inline(always)]
    pub fn clkm_div_num(&mut self) -> CLKM_DIV_NUM_W<0> {
        CLKM_DIV_NUM_W::new(self)
    }
    #[doc = "Bits 8:13 - Fractional clock divider numerator value"]
    #[inline(always)]
    pub fn clkm_div_b(&mut self) -> CLKM_DIV_B_W<8> {
        CLKM_DIV_B_W::new(self)
    }
    #[doc = "Bits 14:19 - Fractional clock divider denominator value"]
    #[inline(always)]
    pub fn clkm_div_a(&mut self) -> CLKM_DIV_A_W<14> {
        CLKM_DIV_A_W::new(self)
    }
    #[doc = "Bit 20 - no public"]
    #[inline(always)]
    pub fn clk_en(&mut self) -> CLK_EN_W<20> {
        CLK_EN_W::new(self)
    }
    #[doc = "Bits 21:22 - Set this bit to enable clk_apll"]
    #[inline(always)]
    pub fn clk_sel(&mut self) -> CLK_SEL_W<21> {
        CLK_SEL_W::new(self)
    }
    #[doc = "Writes raw bits to the register."]
    #[inline(always)]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "configure apb saradc clock\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apb_adc_clkm_conf](index.html) module"]
pub struct APB_ADC_CLKM_CONF_SPEC;
impl crate::RegisterSpec for APB_ADC_CLKM_CONF_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [apb_adc_clkm_conf::R](R) reader structure"]
impl crate::Readable for APB_ADC_CLKM_CONF_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [apb_adc_clkm_conf::W](W) writer structure"]
impl crate::Writable for APB_ADC_CLKM_CONF_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets APB_ADC_CLKM_CONF to value 0x04"]
impl crate::Resettable for APB_ADC_CLKM_CONF_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0x04
    }
}