Module esp32s3::debug_assist::core_1_interrupt_rls

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Expand description

Core1 monitor interrupt enable register

Structs

CORE_1_INTERRUPT_RLS_SPEC

Core1 monitor interrupt enable register

R

Register CORE_1_INTERRUPT_RLS reader

W

Register CORE_1_INTERRUPT_RLS writer

Type Definitions

CORE_1_AREA_DRAM0_0_RD_RLS_R

Field CORE_1_AREA_DRAM0_0_RD_RLS reader - Core1 dram0 area0 read monitor interrupt enable

CORE_1_AREA_DRAM0_0_RD_RLS_W

Field CORE_1_AREA_DRAM0_0_RD_RLS writer - Core1 dram0 area0 read monitor interrupt enable

CORE_1_AREA_DRAM0_0_WR_RLS_R

Field CORE_1_AREA_DRAM0_0_WR_RLS reader - Core1 dram0 area0 write monitor interrupt enable

CORE_1_AREA_DRAM0_0_WR_RLS_W

Field CORE_1_AREA_DRAM0_0_WR_RLS writer - Core1 dram0 area0 write monitor interrupt enable

CORE_1_AREA_DRAM0_1_RD_RLS_R

Field CORE_1_AREA_DRAM0_1_RD_RLS reader - Core1 dram0 area1 read monitor interrupt enable

CORE_1_AREA_DRAM0_1_RD_RLS_W

Field CORE_1_AREA_DRAM0_1_RD_RLS writer - Core1 dram0 area1 read monitor interrupt enable

CORE_1_AREA_DRAM0_1_WR_RLS_R

Field CORE_1_AREA_DRAM0_1_WR_RLS reader - Core1 dram0 area1 write monitor interrupt enable

CORE_1_AREA_DRAM0_1_WR_RLS_W

Field CORE_1_AREA_DRAM0_1_WR_RLS writer - Core1 dram0 area1 write monitor interrupt enable

CORE_1_AREA_PIF_0_RD_RLS_R

Field CORE_1_AREA_PIF_0_RD_RLS reader - Core1 PIF area0 read monitor interrupt enable

CORE_1_AREA_PIF_0_RD_RLS_W

Field CORE_1_AREA_PIF_0_RD_RLS writer - Core1 PIF area0 read monitor interrupt enable

CORE_1_AREA_PIF_0_WR_RLS_R

Field CORE_1_AREA_PIF_0_WR_RLS reader - Core1 PIF area0 write monitor interrupt enable

CORE_1_AREA_PIF_0_WR_RLS_W

Field CORE_1_AREA_PIF_0_WR_RLS writer - Core1 PIF area0 write monitor interrupt enable

CORE_1_AREA_PIF_1_RD_RLS_R

Field CORE_1_AREA_PIF_1_RD_RLS reader - Core1 PIF area1 read monitor interrupt enable

CORE_1_AREA_PIF_1_RD_RLS_W

Field CORE_1_AREA_PIF_1_RD_RLS writer - Core1 PIF area1 read monitor interrupt enable

CORE_1_AREA_PIF_1_WR_RLS_R

Field CORE_1_AREA_PIF_1_WR_RLS reader - Core1 PIF area1 write monitor interrupt enable

CORE_1_AREA_PIF_1_WR_RLS_W

Field CORE_1_AREA_PIF_1_WR_RLS writer - Core1 PIF area1 write monitor interrupt enable

CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_R

Field CORE_1_DRAM0_EXCEPTION_MONITOR_RLS reader - DBUS busy monitor interrupt enbale

CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_W

Field CORE_1_DRAM0_EXCEPTION_MONITOR_RLS writer - DBUS busy monitor interrupt enbale

CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_R

Field CORE_1_IRAM0_EXCEPTION_MONITOR_RLS reader - IBUS busy monitor interrupt enable

CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_W

Field CORE_1_IRAM0_EXCEPTION_MONITOR_RLS writer - IBUS busy monitor interrupt enable

CORE_1_SP_SPILL_MAX_RLS_R

Field CORE_1_SP_SPILL_MAX_RLS reader - Core1 stackpoint underflow monitor interrupt enable

CORE_1_SP_SPILL_MAX_RLS_W

Field CORE_1_SP_SPILL_MAX_RLS writer - Core1 stackpoint underflow monitor interrupt enable

CORE_1_SP_SPILL_MIN_RLS_R

Field CORE_1_SP_SPILL_MIN_RLS reader - Core1 stackpoint overflow monitor interrupt enable

CORE_1_SP_SPILL_MIN_RLS_W

Field CORE_1_SP_SPILL_MIN_RLS writer - Core1 stackpoint overflow monitor interrupt enable