1#[doc = "Register `CONF0` reader"]
2pub type R = crate::R<CONF0_SPEC>;
3#[doc = "Register `CONF0` writer"]
4pub type W = crate::W<CONF0_SPEC>;
5#[doc = "Field `PHY_SEL` reader - Select internal/external PHY"]
6pub type PHY_SEL_R = crate::BitReader;
7#[doc = "Field `PHY_SEL` writer - Select internal/external PHY"]
8pub type PHY_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `EXCHG_PINS_OVERRIDE` reader - Enable software control USB D+ D- exchange"]
10pub type EXCHG_PINS_OVERRIDE_R = crate::BitReader;
11#[doc = "Field `EXCHG_PINS_OVERRIDE` writer - Enable software control USB D+ D- exchange"]
12pub type EXCHG_PINS_OVERRIDE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `EXCHG_PINS` reader - USB D+ D- exchange"]
14pub type EXCHG_PINS_R = crate::BitReader;
15#[doc = "Field `EXCHG_PINS` writer - USB D+ D- exchange"]
16pub type EXCHG_PINS_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `VREFH` reader - Control single-end input high threshold,1.76V to 2V, step 80mV"]
18pub type VREFH_R = crate::FieldReader;
19#[doc = "Field `VREFH` writer - Control single-end input high threshold,1.76V to 2V, step 80mV"]
20pub type VREFH_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21#[doc = "Field `VREFL` reader - Control single-end input low threshold,0.8V to 1.04V, step 80mV"]
22pub type VREFL_R = crate::FieldReader;
23#[doc = "Field `VREFL` writer - Control single-end input low threshold,0.8V to 1.04V, step 80mV"]
24pub type VREFL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25#[doc = "Field `VREF_OVERRIDE` reader - Enable software control input threshold"]
26pub type VREF_OVERRIDE_R = crate::BitReader;
27#[doc = "Field `VREF_OVERRIDE` writer - Enable software control input threshold"]
28pub type VREF_OVERRIDE_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `PAD_PULL_OVERRIDE` reader - Enable software control USB D+ D- pullup pulldown"]
30pub type PAD_PULL_OVERRIDE_R = crate::BitReader;
31#[doc = "Field `PAD_PULL_OVERRIDE` writer - Enable software control USB D+ D- pullup pulldown"]
32pub type PAD_PULL_OVERRIDE_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `DP_PULLUP` reader - Control USB D+ pull up."]
34pub type DP_PULLUP_R = crate::BitReader;
35#[doc = "Field `DP_PULLUP` writer - Control USB D+ pull up."]
36pub type DP_PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `DP_PULLDOWN` reader - Control USB D+ pull down."]
38pub type DP_PULLDOWN_R = crate::BitReader;
39#[doc = "Field `DP_PULLDOWN` writer - Control USB D+ pull down."]
40pub type DP_PULLDOWN_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `DM_PULLUP` reader - Control USB D- pull up."]
42pub type DM_PULLUP_R = crate::BitReader;
43#[doc = "Field `DM_PULLUP` writer - Control USB D- pull up."]
44pub type DM_PULLUP_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `DM_PULLDOWN` reader - Control USB D- pull down."]
46pub type DM_PULLDOWN_R = crate::BitReader;
47#[doc = "Field `DM_PULLDOWN` writer - Control USB D- pull down."]
48pub type DM_PULLDOWN_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `PULLUP_VALUE` reader - Control pull up value."]
50pub type PULLUP_VALUE_R = crate::BitReader;
51#[doc = "Field `PULLUP_VALUE` writer - Control pull up value."]
52pub type PULLUP_VALUE_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `USB_PAD_ENABLE` reader - Enable USB pad function."]
54pub type USB_PAD_ENABLE_R = crate::BitReader;
55#[doc = "Field `USB_PAD_ENABLE` writer - Enable USB pad function."]
56pub type USB_PAD_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `PHY_TX_EDGE_SEL` reader - 0: TX output at clock negedge. 1: Tx output at clock posedge."]
58pub type PHY_TX_EDGE_SEL_R = crate::BitReader;
59#[doc = "Field `PHY_TX_EDGE_SEL` writer - 0: TX output at clock negedge. 1: Tx output at clock posedge."]
60pub type PHY_TX_EDGE_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `USB_JTAG_BRIDGE_EN` reader - Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix."]
62pub type USB_JTAG_BRIDGE_EN_R = crate::BitReader;
63#[doc = "Field `USB_JTAG_BRIDGE_EN` writer - Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix."]
64pub type USB_JTAG_BRIDGE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
65impl R {
66 #[doc = "Bit 0 - Select internal/external PHY"]
67 #[inline(always)]
68 pub fn phy_sel(&self) -> PHY_SEL_R {
69 PHY_SEL_R::new((self.bits & 1) != 0)
70 }
71 #[doc = "Bit 1 - Enable software control USB D+ D- exchange"]
72 #[inline(always)]
73 pub fn exchg_pins_override(&self) -> EXCHG_PINS_OVERRIDE_R {
74 EXCHG_PINS_OVERRIDE_R::new(((self.bits >> 1) & 1) != 0)
75 }
76 #[doc = "Bit 2 - USB D+ D- exchange"]
77 #[inline(always)]
78 pub fn exchg_pins(&self) -> EXCHG_PINS_R {
79 EXCHG_PINS_R::new(((self.bits >> 2) & 1) != 0)
80 }
81 #[doc = "Bits 3:4 - Control single-end input high threshold,1.76V to 2V, step 80mV"]
82 #[inline(always)]
83 pub fn vrefh(&self) -> VREFH_R {
84 VREFH_R::new(((self.bits >> 3) & 3) as u8)
85 }
86 #[doc = "Bits 5:6 - Control single-end input low threshold,0.8V to 1.04V, step 80mV"]
87 #[inline(always)]
88 pub fn vrefl(&self) -> VREFL_R {
89 VREFL_R::new(((self.bits >> 5) & 3) as u8)
90 }
91 #[doc = "Bit 7 - Enable software control input threshold"]
92 #[inline(always)]
93 pub fn vref_override(&self) -> VREF_OVERRIDE_R {
94 VREF_OVERRIDE_R::new(((self.bits >> 7) & 1) != 0)
95 }
96 #[doc = "Bit 8 - Enable software control USB D+ D- pullup pulldown"]
97 #[inline(always)]
98 pub fn pad_pull_override(&self) -> PAD_PULL_OVERRIDE_R {
99 PAD_PULL_OVERRIDE_R::new(((self.bits >> 8) & 1) != 0)
100 }
101 #[doc = "Bit 9 - Control USB D+ pull up."]
102 #[inline(always)]
103 pub fn dp_pullup(&self) -> DP_PULLUP_R {
104 DP_PULLUP_R::new(((self.bits >> 9) & 1) != 0)
105 }
106 #[doc = "Bit 10 - Control USB D+ pull down."]
107 #[inline(always)]
108 pub fn dp_pulldown(&self) -> DP_PULLDOWN_R {
109 DP_PULLDOWN_R::new(((self.bits >> 10) & 1) != 0)
110 }
111 #[doc = "Bit 11 - Control USB D- pull up."]
112 #[inline(always)]
113 pub fn dm_pullup(&self) -> DM_PULLUP_R {
114 DM_PULLUP_R::new(((self.bits >> 11) & 1) != 0)
115 }
116 #[doc = "Bit 12 - Control USB D- pull down."]
117 #[inline(always)]
118 pub fn dm_pulldown(&self) -> DM_PULLDOWN_R {
119 DM_PULLDOWN_R::new(((self.bits >> 12) & 1) != 0)
120 }
121 #[doc = "Bit 13 - Control pull up value."]
122 #[inline(always)]
123 pub fn pullup_value(&self) -> PULLUP_VALUE_R {
124 PULLUP_VALUE_R::new(((self.bits >> 13) & 1) != 0)
125 }
126 #[doc = "Bit 14 - Enable USB pad function."]
127 #[inline(always)]
128 pub fn usb_pad_enable(&self) -> USB_PAD_ENABLE_R {
129 USB_PAD_ENABLE_R::new(((self.bits >> 14) & 1) != 0)
130 }
131 #[doc = "Bit 15 - 0: TX output at clock negedge. 1: Tx output at clock posedge."]
132 #[inline(always)]
133 pub fn phy_tx_edge_sel(&self) -> PHY_TX_EDGE_SEL_R {
134 PHY_TX_EDGE_SEL_R::new(((self.bits >> 15) & 1) != 0)
135 }
136 #[doc = "Bit 16 - Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix."]
137 #[inline(always)]
138 pub fn usb_jtag_bridge_en(&self) -> USB_JTAG_BRIDGE_EN_R {
139 USB_JTAG_BRIDGE_EN_R::new(((self.bits >> 16) & 1) != 0)
140 }
141}
142#[cfg(feature = "impl-register-debug")]
143impl core::fmt::Debug for R {
144 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
145 f.debug_struct("CONF0")
146 .field("phy_sel", &self.phy_sel())
147 .field("exchg_pins_override", &self.exchg_pins_override())
148 .field("exchg_pins", &self.exchg_pins())
149 .field("vrefh", &self.vrefh())
150 .field("vrefl", &self.vrefl())
151 .field("vref_override", &self.vref_override())
152 .field("pad_pull_override", &self.pad_pull_override())
153 .field("dp_pullup", &self.dp_pullup())
154 .field("dp_pulldown", &self.dp_pulldown())
155 .field("dm_pullup", &self.dm_pullup())
156 .field("dm_pulldown", &self.dm_pulldown())
157 .field("pullup_value", &self.pullup_value())
158 .field("usb_pad_enable", &self.usb_pad_enable())
159 .field("phy_tx_edge_sel", &self.phy_tx_edge_sel())
160 .field("usb_jtag_bridge_en", &self.usb_jtag_bridge_en())
161 .finish()
162 }
163}
164impl W {
165 #[doc = "Bit 0 - Select internal/external PHY"]
166 #[inline(always)]
167 pub fn phy_sel(&mut self) -> PHY_SEL_W<CONF0_SPEC> {
168 PHY_SEL_W::new(self, 0)
169 }
170 #[doc = "Bit 1 - Enable software control USB D+ D- exchange"]
171 #[inline(always)]
172 pub fn exchg_pins_override(&mut self) -> EXCHG_PINS_OVERRIDE_W<CONF0_SPEC> {
173 EXCHG_PINS_OVERRIDE_W::new(self, 1)
174 }
175 #[doc = "Bit 2 - USB D+ D- exchange"]
176 #[inline(always)]
177 pub fn exchg_pins(&mut self) -> EXCHG_PINS_W<CONF0_SPEC> {
178 EXCHG_PINS_W::new(self, 2)
179 }
180 #[doc = "Bits 3:4 - Control single-end input high threshold,1.76V to 2V, step 80mV"]
181 #[inline(always)]
182 pub fn vrefh(&mut self) -> VREFH_W<CONF0_SPEC> {
183 VREFH_W::new(self, 3)
184 }
185 #[doc = "Bits 5:6 - Control single-end input low threshold,0.8V to 1.04V, step 80mV"]
186 #[inline(always)]
187 pub fn vrefl(&mut self) -> VREFL_W<CONF0_SPEC> {
188 VREFL_W::new(self, 5)
189 }
190 #[doc = "Bit 7 - Enable software control input threshold"]
191 #[inline(always)]
192 pub fn vref_override(&mut self) -> VREF_OVERRIDE_W<CONF0_SPEC> {
193 VREF_OVERRIDE_W::new(self, 7)
194 }
195 #[doc = "Bit 8 - Enable software control USB D+ D- pullup pulldown"]
196 #[inline(always)]
197 pub fn pad_pull_override(&mut self) -> PAD_PULL_OVERRIDE_W<CONF0_SPEC> {
198 PAD_PULL_OVERRIDE_W::new(self, 8)
199 }
200 #[doc = "Bit 9 - Control USB D+ pull up."]
201 #[inline(always)]
202 pub fn dp_pullup(&mut self) -> DP_PULLUP_W<CONF0_SPEC> {
203 DP_PULLUP_W::new(self, 9)
204 }
205 #[doc = "Bit 10 - Control USB D+ pull down."]
206 #[inline(always)]
207 pub fn dp_pulldown(&mut self) -> DP_PULLDOWN_W<CONF0_SPEC> {
208 DP_PULLDOWN_W::new(self, 10)
209 }
210 #[doc = "Bit 11 - Control USB D- pull up."]
211 #[inline(always)]
212 pub fn dm_pullup(&mut self) -> DM_PULLUP_W<CONF0_SPEC> {
213 DM_PULLUP_W::new(self, 11)
214 }
215 #[doc = "Bit 12 - Control USB D- pull down."]
216 #[inline(always)]
217 pub fn dm_pulldown(&mut self) -> DM_PULLDOWN_W<CONF0_SPEC> {
218 DM_PULLDOWN_W::new(self, 12)
219 }
220 #[doc = "Bit 13 - Control pull up value."]
221 #[inline(always)]
222 pub fn pullup_value(&mut self) -> PULLUP_VALUE_W<CONF0_SPEC> {
223 PULLUP_VALUE_W::new(self, 13)
224 }
225 #[doc = "Bit 14 - Enable USB pad function."]
226 #[inline(always)]
227 pub fn usb_pad_enable(&mut self) -> USB_PAD_ENABLE_W<CONF0_SPEC> {
228 USB_PAD_ENABLE_W::new(self, 14)
229 }
230 #[doc = "Bit 15 - 0: TX output at clock negedge. 1: Tx output at clock posedge."]
231 #[inline(always)]
232 pub fn phy_tx_edge_sel(&mut self) -> PHY_TX_EDGE_SEL_W<CONF0_SPEC> {
233 PHY_TX_EDGE_SEL_W::new(self, 15)
234 }
235 #[doc = "Bit 16 - Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix."]
236 #[inline(always)]
237 pub fn usb_jtag_bridge_en(&mut self) -> USB_JTAG_BRIDGE_EN_W<CONF0_SPEC> {
238 USB_JTAG_BRIDGE_EN_W::new(self, 16)
239 }
240}
241#[doc = "Configure 0 register\n\nYou can [`read`](crate::Reg::read) this register and get [`conf0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
242pub struct CONF0_SPEC;
243impl crate::RegisterSpec for CONF0_SPEC {
244 type Ux = u32;
245}
246#[doc = "`read()` method returns [`conf0::R`](R) reader structure"]
247impl crate::Readable for CONF0_SPEC {}
248#[doc = "`write(|w| ..)` method takes [`conf0::W`](W) writer structure"]
249impl crate::Writable for CONF0_SPEC {
250 type Safety = crate::Unsafe;
251}
252#[doc = "`reset()` method sets CONF0 to value 0x4200"]
253impl crate::Resettable for CONF0_SPEC {
254 const RESET_VALUE: u32 = 0x4200;
255}