esp32s3/usb0/
hcfg.rs

1#[doc = "Register `HCFG` reader"]
2pub type R = crate::R<HCFG_SPEC>;
3#[doc = "Register `HCFG` writer"]
4pub type W = crate::W<HCFG_SPEC>;
5#[doc = "Field `FSLSPCLKSEL` reader - "]
6pub type FSLSPCLKSEL_R = crate::FieldReader;
7#[doc = "Field `FSLSPCLKSEL` writer - "]
8pub type FSLSPCLKSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `FSLSSUPP` reader - "]
10pub type FSLSSUPP_R = crate::BitReader;
11#[doc = "Field `FSLSSUPP` writer - "]
12pub type FSLSSUPP_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `ENA32KHZS` reader - "]
14pub type ENA32KHZS_R = crate::BitReader;
15#[doc = "Field `ENA32KHZS` writer - "]
16pub type ENA32KHZS_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `DESCDMA` reader - "]
18pub type DESCDMA_R = crate::BitReader;
19#[doc = "Field `DESCDMA` writer - "]
20pub type DESCDMA_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `FRLISTEN` reader - "]
22pub type FRLISTEN_R = crate::FieldReader;
23#[doc = "Field `FRLISTEN` writer - "]
24pub type FRLISTEN_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25#[doc = "Field `PERSCHEDENA` reader - "]
26pub type PERSCHEDENA_R = crate::BitReader;
27#[doc = "Field `PERSCHEDENA` writer - "]
28pub type PERSCHEDENA_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `MODECHTIMEN` reader - "]
30pub type MODECHTIMEN_R = crate::BitReader;
31#[doc = "Field `MODECHTIMEN` writer - "]
32pub type MODECHTIMEN_W<'a, REG> = crate::BitWriter<'a, REG>;
33impl R {
34    #[doc = "Bits 0:1"]
35    #[inline(always)]
36    pub fn fslspclksel(&self) -> FSLSPCLKSEL_R {
37        FSLSPCLKSEL_R::new((self.bits & 3) as u8)
38    }
39    #[doc = "Bit 2"]
40    #[inline(always)]
41    pub fn fslssupp(&self) -> FSLSSUPP_R {
42        FSLSSUPP_R::new(((self.bits >> 2) & 1) != 0)
43    }
44    #[doc = "Bit 7"]
45    #[inline(always)]
46    pub fn ena32khzs(&self) -> ENA32KHZS_R {
47        ENA32KHZS_R::new(((self.bits >> 7) & 1) != 0)
48    }
49    #[doc = "Bit 23"]
50    #[inline(always)]
51    pub fn descdma(&self) -> DESCDMA_R {
52        DESCDMA_R::new(((self.bits >> 23) & 1) != 0)
53    }
54    #[doc = "Bits 24:25"]
55    #[inline(always)]
56    pub fn frlisten(&self) -> FRLISTEN_R {
57        FRLISTEN_R::new(((self.bits >> 24) & 3) as u8)
58    }
59    #[doc = "Bit 26"]
60    #[inline(always)]
61    pub fn perschedena(&self) -> PERSCHEDENA_R {
62        PERSCHEDENA_R::new(((self.bits >> 26) & 1) != 0)
63    }
64    #[doc = "Bit 31"]
65    #[inline(always)]
66    pub fn modechtimen(&self) -> MODECHTIMEN_R {
67        MODECHTIMEN_R::new(((self.bits >> 31) & 1) != 0)
68    }
69}
70#[cfg(feature = "impl-register-debug")]
71impl core::fmt::Debug for R {
72    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
73        f.debug_struct("HCFG")
74            .field("fslspclksel", &self.fslspclksel())
75            .field("fslssupp", &self.fslssupp())
76            .field("ena32khzs", &self.ena32khzs())
77            .field("descdma", &self.descdma())
78            .field("frlisten", &self.frlisten())
79            .field("perschedena", &self.perschedena())
80            .field("modechtimen", &self.modechtimen())
81            .finish()
82    }
83}
84impl W {
85    #[doc = "Bits 0:1"]
86    #[inline(always)]
87    pub fn fslspclksel(&mut self) -> FSLSPCLKSEL_W<HCFG_SPEC> {
88        FSLSPCLKSEL_W::new(self, 0)
89    }
90    #[doc = "Bit 2"]
91    #[inline(always)]
92    pub fn fslssupp(&mut self) -> FSLSSUPP_W<HCFG_SPEC> {
93        FSLSSUPP_W::new(self, 2)
94    }
95    #[doc = "Bit 7"]
96    #[inline(always)]
97    pub fn ena32khzs(&mut self) -> ENA32KHZS_W<HCFG_SPEC> {
98        ENA32KHZS_W::new(self, 7)
99    }
100    #[doc = "Bit 23"]
101    #[inline(always)]
102    pub fn descdma(&mut self) -> DESCDMA_W<HCFG_SPEC> {
103        DESCDMA_W::new(self, 23)
104    }
105    #[doc = "Bits 24:25"]
106    #[inline(always)]
107    pub fn frlisten(&mut self) -> FRLISTEN_W<HCFG_SPEC> {
108        FRLISTEN_W::new(self, 24)
109    }
110    #[doc = "Bit 26"]
111    #[inline(always)]
112    pub fn perschedena(&mut self) -> PERSCHEDENA_W<HCFG_SPEC> {
113        PERSCHEDENA_W::new(self, 26)
114    }
115    #[doc = "Bit 31"]
116    #[inline(always)]
117    pub fn modechtimen(&mut self) -> MODECHTIMEN_W<HCFG_SPEC> {
118        MODECHTIMEN_W::new(self, 31)
119    }
120}
121#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`hcfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hcfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
122pub struct HCFG_SPEC;
123impl crate::RegisterSpec for HCFG_SPEC {
124    type Ux = u32;
125}
126#[doc = "`read()` method returns [`hcfg::R`](R) reader structure"]
127impl crate::Readable for HCFG_SPEC {}
128#[doc = "`write(|w| ..)` method takes [`hcfg::W`](W) writer structure"]
129impl crate::Writable for HCFG_SPEC {
130    type Safety = crate::Unsafe;
131}
132#[doc = "`reset()` method sets HCFG to value 0"]
133impl crate::Resettable for HCFG_SPEC {}
esp32s3/usb0/hcfg.rs

esp32s3/usb0/
hcfg.rs
