1#[repr(C)]
2#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5 conf0: CONF0,
6 int_raw: INT_RAW,
7 int_st: INT_ST,
8 int_ena: INT_ENA,
9 int_clr: INT_CLR,
10 app_int_set: APP_INT_SET,
11 conf1: CONF1,
12 state0: STATE0,
13 state1: STATE1,
14 escape_conf: ESCAPE_CONF,
15 hung_conf: HUNG_CONF,
16 ack_num: ACK_NUM,
17 rx_head: RX_HEAD,
18 quick_sent: QUICK_SENT,
19 reg_q: [REG_Q; 7],
20 esc_conf: [ESC_CONF; 4],
21 pkt_thres: PKT_THRES,
22 date: DATE,
23}
24impl RegisterBlock {
25 #[doc = "0x00 - UHCI configuration register"]
26 #[inline(always)]
27 pub const fn conf0(&self) -> &CONF0 {
28 &self.conf0
29 }
30 #[doc = "0x04 - Raw interrupt status"]
31 #[inline(always)]
32 pub const fn int_raw(&self) -> &INT_RAW {
33 &self.int_raw
34 }
35 #[doc = "0x08 - Masked interrupt status"]
36 #[inline(always)]
37 pub const fn int_st(&self) -> &INT_ST {
38 &self.int_st
39 }
40 #[doc = "0x0c - Interrupt enable bits"]
41 #[inline(always)]
42 pub const fn int_ena(&self) -> &INT_ENA {
43 &self.int_ena
44 }
45 #[doc = "0x10 - Interrupt clear bits"]
46 #[inline(always)]
47 pub const fn int_clr(&self) -> &INT_CLR {
48 &self.int_clr
49 }
50 #[doc = "0x14 - Software interrupt trigger source"]
51 #[inline(always)]
52 pub const fn app_int_set(&self) -> &APP_INT_SET {
53 &self.app_int_set
54 }
55 #[doc = "0x18 - UHCI configuration register"]
56 #[inline(always)]
57 pub const fn conf1(&self) -> &CONF1 {
58 &self.conf1
59 }
60 #[doc = "0x1c - UHCI receive status"]
61 #[inline(always)]
62 pub const fn state0(&self) -> &STATE0 {
63 &self.state0
64 }
65 #[doc = "0x20 - UHCI transmit status"]
66 #[inline(always)]
67 pub const fn state1(&self) -> &STATE1 {
68 &self.state1
69 }
70 #[doc = "0x24 - Escape character configuration"]
71 #[inline(always)]
72 pub const fn escape_conf(&self) -> &ESCAPE_CONF {
73 &self.escape_conf
74 }
75 #[doc = "0x28 - Timeout configuration"]
76 #[inline(always)]
77 pub const fn hung_conf(&self) -> &HUNG_CONF {
78 &self.hung_conf
79 }
80 #[doc = "0x2c - UHCI ACK number configuration"]
81 #[inline(always)]
82 pub const fn ack_num(&self) -> &ACK_NUM {
83 &self.ack_num
84 }
85 #[doc = "0x30 - UHCI packet header register"]
86 #[inline(always)]
87 pub const fn rx_head(&self) -> &RX_HEAD {
88 &self.rx_head
89 }
90 #[doc = "0x34 - UHCI quick send configuration register"]
91 #[inline(always)]
92 pub const fn quick_sent(&self) -> &QUICK_SENT {
93 &self.quick_sent
94 }
95 #[doc = "0x38..0x70 - Cluster REG_Q%s, containing REG_Q?_WORD0, REG_Q?_WORD1"]
96 #[inline(always)]
97 pub const fn reg_q(&self, n: usize) -> ®_Q {
98 &self.reg_q[n]
99 }
100 #[doc = "Iterator for array of:"]
101 #[doc = "0x38..0x70 - Cluster REG_Q%s, containing REG_Q?_WORD0, REG_Q?_WORD1"]
102 #[inline(always)]
103 pub fn reg_q_iter(&self) -> impl Iterator<Item = ®_Q> {
104 self.reg_q.iter()
105 }
106 #[doc = "0x70..0x80 - Escape sequence configuration register %s"]
107 #[inline(always)]
108 pub const fn esc_conf(&self, n: usize) -> &ESC_CONF {
109 &self.esc_conf[n]
110 }
111 #[doc = "Iterator for array of:"]
112 #[doc = "0x70..0x80 - Escape sequence configuration register %s"]
113 #[inline(always)]
114 pub fn esc_conf_iter(&self) -> impl Iterator<Item = &ESC_CONF> {
115 self.esc_conf.iter()
116 }
117 #[doc = "0x80 - Configure register for packet length"]
118 #[inline(always)]
119 pub const fn pkt_thres(&self) -> &PKT_THRES {
120 &self.pkt_thres
121 }
122 #[doc = "0x84 - UHCI version control register"]
123 #[inline(always)]
124 pub const fn date(&self) -> &DATE {
125 &self.date
126 }
127}
128#[doc = "CONF0 (rw) register accessor: UHCI configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`conf0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf0`] module"]
129pub type CONF0 = crate::Reg<conf0::CONF0_SPEC>;
130#[doc = "UHCI configuration register"]
131pub mod conf0;
132#[doc = "INT_RAW (rw) register accessor: Raw interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_raw::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"]
133pub type INT_RAW = crate::Reg<int_raw::INT_RAW_SPEC>;
134#[doc = "Raw interrupt status"]
135pub mod int_raw;
136#[doc = "INT_ST (r) register accessor: Masked interrupt status\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"]
137pub type INT_ST = crate::Reg<int_st::INT_ST_SPEC>;
138#[doc = "Masked interrupt status"]
139pub mod int_st;
140#[doc = "INT_ENA (rw) register accessor: Interrupt enable bits\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"]
141pub type INT_ENA = crate::Reg<int_ena::INT_ENA_SPEC>;
142#[doc = "Interrupt enable bits"]
143pub mod int_ena;
144#[doc = "INT_CLR (w) register accessor: Interrupt clear bits\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
145pub type INT_CLR = crate::Reg<int_clr::INT_CLR_SPEC>;
146#[doc = "Interrupt clear bits"]
147pub mod int_clr;
148#[doc = "APP_INT_SET (w) register accessor: Software interrupt trigger source\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`app_int_set::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@app_int_set`] module"]
149pub type APP_INT_SET = crate::Reg<app_int_set::APP_INT_SET_SPEC>;
150#[doc = "Software interrupt trigger source"]
151pub mod app_int_set;
152#[doc = "CONF1 (rw) register accessor: UHCI configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`conf1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`conf1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@conf1`] module"]
153pub type CONF1 = crate::Reg<conf1::CONF1_SPEC>;
154#[doc = "UHCI configuration register"]
155pub mod conf1;
156#[doc = "STATE0 (r) register accessor: UHCI receive status\n\nYou can [`read`](crate::Reg::read) this register and get [`state0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state0`] module"]
157pub type STATE0 = crate::Reg<state0::STATE0_SPEC>;
158#[doc = "UHCI receive status"]
159pub mod state0;
160#[doc = "STATE1 (r) register accessor: UHCI transmit status\n\nYou can [`read`](crate::Reg::read) this register and get [`state1::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state1`] module"]
161pub type STATE1 = crate::Reg<state1::STATE1_SPEC>;
162#[doc = "UHCI transmit status"]
163pub mod state1;
164#[doc = "ESCAPE_CONF (rw) register accessor: Escape character configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`escape_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`escape_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@escape_conf`] module"]
165pub type ESCAPE_CONF = crate::Reg<escape_conf::ESCAPE_CONF_SPEC>;
166#[doc = "Escape character configuration"]
167pub mod escape_conf;
168#[doc = "HUNG_CONF (rw) register accessor: Timeout configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`hung_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`hung_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hung_conf`] module"]
169pub type HUNG_CONF = crate::Reg<hung_conf::HUNG_CONF_SPEC>;
170#[doc = "Timeout configuration"]
171pub mod hung_conf;
172#[doc = "ACK_NUM (rw) register accessor: UHCI ACK number configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`ack_num::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ack_num::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ack_num`] module"]
173pub type ACK_NUM = crate::Reg<ack_num::ACK_NUM_SPEC>;
174#[doc = "UHCI ACK number configuration"]
175pub mod ack_num;
176#[doc = "RX_HEAD (r) register accessor: UHCI packet header register\n\nYou can [`read`](crate::Reg::read) this register and get [`rx_head::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rx_head`] module"]
177pub type RX_HEAD = crate::Reg<rx_head::RX_HEAD_SPEC>;
178#[doc = "UHCI packet header register"]
179pub mod rx_head;
180#[doc = "QUICK_SENT (rw) register accessor: UHCI quick send configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`quick_sent::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`quick_sent::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@quick_sent`] module"]
181pub type QUICK_SENT = crate::Reg<quick_sent::QUICK_SENT_SPEC>;
182#[doc = "UHCI quick send configuration register"]
183pub mod quick_sent;
184#[doc = "Cluster REG_Q%s, containing REG_Q?_WORD0, REG_Q?_WORD1"]
185pub use self::reg_q::REG_Q;
186#[doc = r"Cluster"]
187#[doc = "Cluster REG_Q%s, containing REG_Q?_WORD0, REG_Q?_WORD1"]
188pub mod reg_q;
189#[doc = "ESC_CONF (rw) register accessor: Escape sequence configuration register %s\n\nYou can [`read`](crate::Reg::read) this register and get [`esc_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esc_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@esc_conf`] module"]
190pub type ESC_CONF = crate::Reg<esc_conf::ESC_CONF_SPEC>;
191#[doc = "Escape sequence configuration register %s"]
192pub mod esc_conf;
193#[doc = "PKT_THRES (rw) register accessor: Configure register for packet length\n\nYou can [`read`](crate::Reg::read) this register and get [`pkt_thres::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pkt_thres::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pkt_thres`] module"]
194pub type PKT_THRES = crate::Reg<pkt_thres::PKT_THRES_SPEC>;
195#[doc = "Configure register for packet length"]
196pub mod pkt_thres;
197#[doc = "DATE (rw) register accessor: UHCI version control register\n\nYou can [`read`](crate::Reg::read) this register and get [`date::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`date::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@date`] module"]
198pub type DATE = crate::Reg<date::DATE_SPEC>;
199#[doc = "UHCI version control register"]
200pub mod date;