esp32s3/sensitive/
core_0_pif_pms_constrain_9.rs

1#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_9` reader"]
2pub type R = crate::R<CORE_0_PIF_PMS_CONSTRAIN_9_SPEC>;
3#[doc = "Register `CORE_0_PIF_PMS_CONSTRAIN_9` writer"]
4pub type W = crate::W<CORE_0_PIF_PMS_CONSTRAIN_9_SPEC>;
5#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0` reader - RTCFast memory split address in world 0 for core0."]
6pub type CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_R = crate::FieldReader<u16>;
7#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0` writer - RTCFast memory split address in world 0 for core0."]
8pub type CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_W<'a, REG> =
9    crate::FieldWriter<'a, REG, 11, u16>;
10#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1` reader - RTCFast memory split address in world 1 for core0."]
11pub type CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_R = crate::FieldReader<u16>;
12#[doc = "Field `CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1` writer - RTCFast memory split address in world 1 for core0."]
13pub type CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_W<'a, REG> =
14    crate::FieldWriter<'a, REG, 11, u16>;
15impl R {
16    #[doc = "Bits 0:10 - RTCFast memory split address in world 0 for core0."]
17    #[inline(always)]
18    pub fn core_0_pif_pms_constrain_rtcfast_spltaddr_world_0(
19        &self,
20    ) -> CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_R {
21        CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_R::new((self.bits & 0x07ff) as u16)
22    }
23    #[doc = "Bits 11:21 - RTCFast memory split address in world 1 for core0."]
24    #[inline(always)]
25    pub fn core_0_pif_pms_constrain_rtcfast_spltaddr_world_1(
26        &self,
27    ) -> CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_R {
28        CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_R::new(
29            ((self.bits >> 11) & 0x07ff) as u16,
30        )
31    }
32}
33#[cfg(feature = "impl-register-debug")]
34impl core::fmt::Debug for R {
35    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
36        f.debug_struct("CORE_0_PIF_PMS_CONSTRAIN_9")
37            .field(
38                "core_0_pif_pms_constrain_rtcfast_spltaddr_world_0",
39                &self.core_0_pif_pms_constrain_rtcfast_spltaddr_world_0(),
40            )
41            .field(
42                "core_0_pif_pms_constrain_rtcfast_spltaddr_world_1",
43                &self.core_0_pif_pms_constrain_rtcfast_spltaddr_world_1(),
44            )
45            .finish()
46    }
47}
48impl W {
49    #[doc = "Bits 0:10 - RTCFast memory split address in world 0 for core0."]
50    #[inline(always)]
51    pub fn core_0_pif_pms_constrain_rtcfast_spltaddr_world_0(
52        &mut self,
53    ) -> CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_W<CORE_0_PIF_PMS_CONSTRAIN_9_SPEC> {
54        CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_W::new(self, 0)
55    }
56    #[doc = "Bits 11:21 - RTCFast memory split address in world 1 for core0."]
57    #[inline(always)]
58    pub fn core_0_pif_pms_constrain_rtcfast_spltaddr_world_1(
59        &mut self,
60    ) -> CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_W<CORE_0_PIF_PMS_CONSTRAIN_9_SPEC> {
61        CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_W::new(self, 11)
62    }
63}
64#[doc = "Core0 access peripherals permission configuration register 9.\n\nYou can [`read`](crate::Reg::read) this register and get [`core_0_pif_pms_constrain_9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core_0_pif_pms_constrain_9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
65pub struct CORE_0_PIF_PMS_CONSTRAIN_9_SPEC;
66impl crate::RegisterSpec for CORE_0_PIF_PMS_CONSTRAIN_9_SPEC {
67    type Ux = u32;
68}
69#[doc = "`read()` method returns [`core_0_pif_pms_constrain_9::R`](R) reader structure"]
70impl crate::Readable for CORE_0_PIF_PMS_CONSTRAIN_9_SPEC {}
71#[doc = "`write(|w| ..)` method takes [`core_0_pif_pms_constrain_9::W`](W) writer structure"]
72impl crate::Writable for CORE_0_PIF_PMS_CONSTRAIN_9_SPEC {
73    type Safety = crate::Unsafe;
74}
75#[doc = "`reset()` method sets CORE_0_PIF_PMS_CONSTRAIN_9 to value 0x003f_ffff"]
76impl crate::Resettable for CORE_0_PIF_PMS_CONSTRAIN_9_SPEC {
77    const RESET_VALUE: u32 = 0x003f_ffff;
78}
esp32s3/sensitive/core_0_pif_pms_constrain_9.rs

esp32s3/sensitive/
core_0_pif_pms_constrain_9.rs
