esp32s3/rtc_cntl/
cocpu_ctrl.rs

1#[doc = "Register `COCPU_CTRL` reader"]
2pub type R = crate::R<COCPU_CTRL_SPEC>;
3#[doc = "Register `COCPU_CTRL` writer"]
4pub type W = crate::W<COCPU_CTRL_SPEC>;
5#[doc = "Field `COCPU_CLK_FO` reader - cocpu clk force on"]
6pub type COCPU_CLK_FO_R = crate::BitReader;
7#[doc = "Field `COCPU_CLK_FO` writer - cocpu clk force on"]
8pub type COCPU_CLK_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `COCPU_START_2_RESET_DIS` reader - time from start cocpu to pull down reset"]
10pub type COCPU_START_2_RESET_DIS_R = crate::FieldReader;
11#[doc = "Field `COCPU_START_2_RESET_DIS` writer - time from start cocpu to pull down reset"]
12pub type COCPU_START_2_RESET_DIS_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
13#[doc = "Field `COCPU_START_2_INTR_EN` reader - time from start cocpu to give start interrupt"]
14pub type COCPU_START_2_INTR_EN_R = crate::FieldReader;
15#[doc = "Field `COCPU_START_2_INTR_EN` writer - time from start cocpu to give start interrupt"]
16pub type COCPU_START_2_INTR_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
17#[doc = "Field `COCPU_SHUT` reader - to shut cocpu"]
18pub type COCPU_SHUT_R = crate::BitReader;
19#[doc = "Field `COCPU_SHUT` writer - to shut cocpu"]
20pub type COCPU_SHUT_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `COCPU_SHUT_2_CLK_DIS` reader - time from shut cocpu to disable clk"]
22pub type COCPU_SHUT_2_CLK_DIS_R = crate::FieldReader;
23#[doc = "Field `COCPU_SHUT_2_CLK_DIS` writer - time from shut cocpu to disable clk"]
24pub type COCPU_SHUT_2_CLK_DIS_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
25#[doc = "Field `COCPU_SHUT_RESET_EN` reader - to reset cocpu"]
26pub type COCPU_SHUT_RESET_EN_R = crate::BitReader;
27#[doc = "Field `COCPU_SHUT_RESET_EN` writer - to reset cocpu"]
28pub type COCPU_SHUT_RESET_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `COCPU_SEL` reader - 1: old ULP 0: new riscV"]
30pub type COCPU_SEL_R = crate::BitReader;
31#[doc = "Field `COCPU_SEL` writer - 1: old ULP 0: new riscV"]
32pub type COCPU_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `COCPU_DONE_FORCE` reader - 1: select riscv done 0: select ulp done"]
34pub type COCPU_DONE_FORCE_R = crate::BitReader;
35#[doc = "Field `COCPU_DONE_FORCE` writer - 1: select riscv done 0: select ulp done"]
36pub type COCPU_DONE_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `COCPU_DONE` reader - done signal used by riscv to control timer."]
38pub type COCPU_DONE_R = crate::BitReader;
39#[doc = "Field `COCPU_DONE` writer - done signal used by riscv to control timer."]
40pub type COCPU_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `COCPU_SW_INT_TRIGGER` writer - trigger cocpu register interrupt"]
42pub type COCPU_SW_INT_TRIGGER_W<'a, REG> = crate::BitWriter<'a, REG>;
43#[doc = "Field `COCPU_CLKGATE_EN` reader - open ulp-riscv clk gate"]
44pub type COCPU_CLKGATE_EN_R = crate::BitReader;
45#[doc = "Field `COCPU_CLKGATE_EN` writer - open ulp-riscv clk gate"]
46pub type COCPU_CLKGATE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
47impl R {
48    #[doc = "Bit 0 - cocpu clk force on"]
49    #[inline(always)]
50    pub fn cocpu_clk_fo(&self) -> COCPU_CLK_FO_R {
51        COCPU_CLK_FO_R::new((self.bits & 1) != 0)
52    }
53    #[doc = "Bits 1:6 - time from start cocpu to pull down reset"]
54    #[inline(always)]
55    pub fn cocpu_start_2_reset_dis(&self) -> COCPU_START_2_RESET_DIS_R {
56        COCPU_START_2_RESET_DIS_R::new(((self.bits >> 1) & 0x3f) as u8)
57    }
58    #[doc = "Bits 7:12 - time from start cocpu to give start interrupt"]
59    #[inline(always)]
60    pub fn cocpu_start_2_intr_en(&self) -> COCPU_START_2_INTR_EN_R {
61        COCPU_START_2_INTR_EN_R::new(((self.bits >> 7) & 0x3f) as u8)
62    }
63    #[doc = "Bit 13 - to shut cocpu"]
64    #[inline(always)]
65    pub fn cocpu_shut(&self) -> COCPU_SHUT_R {
66        COCPU_SHUT_R::new(((self.bits >> 13) & 1) != 0)
67    }
68    #[doc = "Bits 14:21 - time from shut cocpu to disable clk"]
69    #[inline(always)]
70    pub fn cocpu_shut_2_clk_dis(&self) -> COCPU_SHUT_2_CLK_DIS_R {
71        COCPU_SHUT_2_CLK_DIS_R::new(((self.bits >> 14) & 0xff) as u8)
72    }
73    #[doc = "Bit 22 - to reset cocpu"]
74    #[inline(always)]
75    pub fn cocpu_shut_reset_en(&self) -> COCPU_SHUT_RESET_EN_R {
76        COCPU_SHUT_RESET_EN_R::new(((self.bits >> 22) & 1) != 0)
77    }
78    #[doc = "Bit 23 - 1: old ULP 0: new riscV"]
79    #[inline(always)]
80    pub fn cocpu_sel(&self) -> COCPU_SEL_R {
81        COCPU_SEL_R::new(((self.bits >> 23) & 1) != 0)
82    }
83    #[doc = "Bit 24 - 1: select riscv done 0: select ulp done"]
84    #[inline(always)]
85    pub fn cocpu_done_force(&self) -> COCPU_DONE_FORCE_R {
86        COCPU_DONE_FORCE_R::new(((self.bits >> 24) & 1) != 0)
87    }
88    #[doc = "Bit 25 - done signal used by riscv to control timer."]
89    #[inline(always)]
90    pub fn cocpu_done(&self) -> COCPU_DONE_R {
91        COCPU_DONE_R::new(((self.bits >> 25) & 1) != 0)
92    }
93    #[doc = "Bit 27 - open ulp-riscv clk gate"]
94    #[inline(always)]
95    pub fn cocpu_clkgate_en(&self) -> COCPU_CLKGATE_EN_R {
96        COCPU_CLKGATE_EN_R::new(((self.bits >> 27) & 1) != 0)
97    }
98}
99#[cfg(feature = "impl-register-debug")]
100impl core::fmt::Debug for R {
101    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
102        f.debug_struct("COCPU_CTRL")
103            .field("cocpu_clk_fo", &self.cocpu_clk_fo())
104            .field("cocpu_start_2_reset_dis", &self.cocpu_start_2_reset_dis())
105            .field("cocpu_start_2_intr_en", &self.cocpu_start_2_intr_en())
106            .field("cocpu_shut", &self.cocpu_shut())
107            .field("cocpu_shut_2_clk_dis", &self.cocpu_shut_2_clk_dis())
108            .field("cocpu_shut_reset_en", &self.cocpu_shut_reset_en())
109            .field("cocpu_sel", &self.cocpu_sel())
110            .field("cocpu_done_force", &self.cocpu_done_force())
111            .field("cocpu_done", &self.cocpu_done())
112            .field("cocpu_clkgate_en", &self.cocpu_clkgate_en())
113            .finish()
114    }
115}
116impl W {
117    #[doc = "Bit 0 - cocpu clk force on"]
118    #[inline(always)]
119    pub fn cocpu_clk_fo(&mut self) -> COCPU_CLK_FO_W<COCPU_CTRL_SPEC> {
120        COCPU_CLK_FO_W::new(self, 0)
121    }
122    #[doc = "Bits 1:6 - time from start cocpu to pull down reset"]
123    #[inline(always)]
124    pub fn cocpu_start_2_reset_dis(&mut self) -> COCPU_START_2_RESET_DIS_W<COCPU_CTRL_SPEC> {
125        COCPU_START_2_RESET_DIS_W::new(self, 1)
126    }
127    #[doc = "Bits 7:12 - time from start cocpu to give start interrupt"]
128    #[inline(always)]
129    pub fn cocpu_start_2_intr_en(&mut self) -> COCPU_START_2_INTR_EN_W<COCPU_CTRL_SPEC> {
130        COCPU_START_2_INTR_EN_W::new(self, 7)
131    }
132    #[doc = "Bit 13 - to shut cocpu"]
133    #[inline(always)]
134    pub fn cocpu_shut(&mut self) -> COCPU_SHUT_W<COCPU_CTRL_SPEC> {
135        COCPU_SHUT_W::new(self, 13)
136    }
137    #[doc = "Bits 14:21 - time from shut cocpu to disable clk"]
138    #[inline(always)]
139    pub fn cocpu_shut_2_clk_dis(&mut self) -> COCPU_SHUT_2_CLK_DIS_W<COCPU_CTRL_SPEC> {
140        COCPU_SHUT_2_CLK_DIS_W::new(self, 14)
141    }
142    #[doc = "Bit 22 - to reset cocpu"]
143    #[inline(always)]
144    pub fn cocpu_shut_reset_en(&mut self) -> COCPU_SHUT_RESET_EN_W<COCPU_CTRL_SPEC> {
145        COCPU_SHUT_RESET_EN_W::new(self, 22)
146    }
147    #[doc = "Bit 23 - 1: old ULP 0: new riscV"]
148    #[inline(always)]
149    pub fn cocpu_sel(&mut self) -> COCPU_SEL_W<COCPU_CTRL_SPEC> {
150        COCPU_SEL_W::new(self, 23)
151    }
152    #[doc = "Bit 24 - 1: select riscv done 0: select ulp done"]
153    #[inline(always)]
154    pub fn cocpu_done_force(&mut self) -> COCPU_DONE_FORCE_W<COCPU_CTRL_SPEC> {
155        COCPU_DONE_FORCE_W::new(self, 24)
156    }
157    #[doc = "Bit 25 - done signal used by riscv to control timer."]
158    #[inline(always)]
159    pub fn cocpu_done(&mut self) -> COCPU_DONE_W<COCPU_CTRL_SPEC> {
160        COCPU_DONE_W::new(self, 25)
161    }
162    #[doc = "Bit 26 - trigger cocpu register interrupt"]
163    #[inline(always)]
164    pub fn cocpu_sw_int_trigger(&mut self) -> COCPU_SW_INT_TRIGGER_W<COCPU_CTRL_SPEC> {
165        COCPU_SW_INT_TRIGGER_W::new(self, 26)
166    }
167    #[doc = "Bit 27 - open ulp-riscv clk gate"]
168    #[inline(always)]
169    pub fn cocpu_clkgate_en(&mut self) -> COCPU_CLKGATE_EN_W<COCPU_CTRL_SPEC> {
170        COCPU_CLKGATE_EN_W::new(self, 27)
171    }
172}
173#[doc = "configure ulp-riscv\n\nYou can [`read`](crate::Reg::read) this register and get [`cocpu_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cocpu_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
174pub struct COCPU_CTRL_SPEC;
175impl crate::RegisterSpec for COCPU_CTRL_SPEC {
176    type Ux = u32;
177}
178#[doc = "`read()` method returns [`cocpu_ctrl::R`](R) reader structure"]
179impl crate::Readable for COCPU_CTRL_SPEC {}
180#[doc = "`write(|w| ..)` method takes [`cocpu_ctrl::W`](W) writer structure"]
181impl crate::Writable for COCPU_CTRL_SPEC {
182    type Safety = crate::Unsafe;
183}
184#[doc = "`reset()` method sets COCPU_CTRL to value 0x008a_0810"]
185impl crate::Resettable for COCPU_CTRL_SPEC {
186    const RESET_VALUE: u32 = 0x008a_0810;
187}
esp32s3/rtc_cntl/cocpu_ctrl.rs

esp32s3/rtc_cntl/
cocpu_ctrl.rs
