esp32s3/extmem/
core0_acs_cache_int_clr.rs

1#[doc = "Register `CORE0_ACS_CACHE_INT_CLR` writer"]
2pub type W = crate::W<CORE0_ACS_CACHE_INT_CLR_SPEC>;
3#[doc = "Field `CORE0_IBUS_ACS_MSK_IC` writer - The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access."]
4pub type CORE0_IBUS_ACS_MSK_IC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `CORE0_IBUS_WR_IC` writer - The bit is used to clear interrupt by ibus trying to write icache"]
6pub type CORE0_IBUS_WR_IC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `CORE0_IBUS_REJECT` writer - The bit is used to clear interrupt by authentication fail."]
8pub type CORE0_IBUS_REJECT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `CORE0_DBUS_ACS_MSK_DC` writer - The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access."]
10pub type CORE0_DBUS_ACS_MSK_DC_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `CORE0_DBUS_REJECT` writer - The bit is used to clear interrupt by authentication fail."]
12pub type CORE0_DBUS_REJECT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[cfg(feature = "impl-register-debug")]
14impl core::fmt::Debug for crate::generic::Reg<CORE0_ACS_CACHE_INT_CLR_SPEC> {
15    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
16        write!(f, "(not readable)")
17    }
18}
19impl W {
20    #[doc = "Bit 0 - The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access."]
21    #[inline(always)]
22    pub fn core0_ibus_acs_msk_ic(
23        &mut self,
24    ) -> CORE0_IBUS_ACS_MSK_IC_W<CORE0_ACS_CACHE_INT_CLR_SPEC> {
25        CORE0_IBUS_ACS_MSK_IC_W::new(self, 0)
26    }
27    #[doc = "Bit 1 - The bit is used to clear interrupt by ibus trying to write icache"]
28    #[inline(always)]
29    pub fn core0_ibus_wr_ic(&mut self) -> CORE0_IBUS_WR_IC_W<CORE0_ACS_CACHE_INT_CLR_SPEC> {
30        CORE0_IBUS_WR_IC_W::new(self, 1)
31    }
32    #[doc = "Bit 2 - The bit is used to clear interrupt by authentication fail."]
33    #[inline(always)]
34    pub fn core0_ibus_reject(&mut self) -> CORE0_IBUS_REJECT_W<CORE0_ACS_CACHE_INT_CLR_SPEC> {
35        CORE0_IBUS_REJECT_W::new(self, 2)
36    }
37    #[doc = "Bit 3 - The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access."]
38    #[inline(always)]
39    pub fn core0_dbus_acs_msk_dc(
40        &mut self,
41    ) -> CORE0_DBUS_ACS_MSK_DC_W<CORE0_ACS_CACHE_INT_CLR_SPEC> {
42        CORE0_DBUS_ACS_MSK_DC_W::new(self, 3)
43    }
44    #[doc = "Bit 4 - The bit is used to clear interrupt by authentication fail."]
45    #[inline(always)]
46    pub fn core0_dbus_reject(&mut self) -> CORE0_DBUS_REJECT_W<CORE0_ACS_CACHE_INT_CLR_SPEC> {
47        CORE0_DBUS_REJECT_W::new(self, 4)
48    }
49}
50#[doc = "******* Description ***********\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`core0_acs_cache_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
51pub struct CORE0_ACS_CACHE_INT_CLR_SPEC;
52impl crate::RegisterSpec for CORE0_ACS_CACHE_INT_CLR_SPEC {
53    type Ux = u32;
54}
55#[doc = "`write(|w| ..)` method takes [`core0_acs_cache_int_clr::W`](W) writer structure"]
56impl crate::Writable for CORE0_ACS_CACHE_INT_CLR_SPEC {
57    type Safety = crate::Unsafe;
58    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x1f;
59}
60#[doc = "`reset()` method sets CORE0_ACS_CACHE_INT_CLR to value 0"]
61impl crate::Resettable for CORE0_ACS_CACHE_INT_CLR_SPEC {}
esp32s3/extmem/core0_acs_cache_int_clr.rs

esp32s3/extmem/
core0_acs_cache_int_clr.rs
