esp32s3

Module extmem

Source
Expand description

External Memory

Modules§

cache_acs_cnt_clr
******* Description ***********
cache_bridge_arbiter_ctrl
******* Description ***********
cache_conf_misc
******* Description ***********
cache_encrypt_decrypt_clk_force_on
******* Description ***********
cache_encrypt_decrypt_record_disable
******* Description ***********
cache_ilg_int_clr
******* Description ***********
cache_ilg_int_ena
******* Description ***********
cache_ilg_int_st
******* Description ***********
cache_mmu_fault_content
******* Description ***********
cache_mmu_fault_vaddr
******* Description ***********
cache_mmu_owner
******* Description ***********
cache_mmu_power_ctrl
******* Description ***********
cache_preload_int_ctrl
******* Description ***********
cache_request
******* Description ***********
cache_state
******* Description ***********
cache_sync_int_ctrl
******* Description ***********
cache_tag_content
******* Description ***********
cache_tag_object_ctrl
******* Description ***********
cache_tag_way_object
******* Description ***********
cache_vaddr
******* Description ***********
cache_wrap_around_ctrl
******* Description ***********
clock_gate
******* Description ***********
core0_acs_cache_int_clr
******* Description ***********
core0_acs_cache_int_ena
******* Description ***********
core0_acs_cache_int_st
******* Description ***********
core0_dbus_reject_st
******* Description ***********
core0_dbus_reject_vaddr
******* Description ***********
core0_ibus_reject_st
******* Description ***********
core0_ibus_reject_vaddr
******* Description ***********
core1_acs_cache_int_clr
******* Description ***********
core1_acs_cache_int_ena
******* Description ***********
core1_acs_cache_int_st
******* Description ***********
core1_dbus_reject_st
******* Description ***********
core1_dbus_reject_vaddr
******* Description ***********
core1_ibus_reject_st
******* Description ***********
core1_ibus_reject_vaddr
******* Description ***********
date
******* Description ***********
dbus_acs_cnt
******* Description ***********
dbus_acs_flash_miss_cnt
******* Description ***********
dbus_acs_spiram_miss_cnt
******* Description ***********
dbus_to_flash_end_vaddr
******* Description ***********
dbus_to_flash_start_vaddr
******* Description ***********
dcache_atomic_operate_ena
******* Description ***********
dcache_autoload_ctrl
******* Description ***********
dcache_autoload_sct0_addr
******* Description ***********
dcache_autoload_sct0_size
******* Description ***********
dcache_autoload_sct1_addr
******* Description ***********
dcache_autoload_sct1_size
******* Description ***********
dcache_ctrl
******* Description ***********
dcache_ctrl1
******* Description ***********
dcache_freeze
******* Description ***********
dcache_lock_addr
******* Description ***********
dcache_lock_ctrl
******* Description ***********
dcache_lock_size
******* Description ***********
dcache_occupy_addr
******* Description ***********
dcache_occupy_ctrl
******* Description ***********
dcache_occupy_size
******* Description ***********
dcache_preload_addr
******* Description ***********
dcache_preload_ctrl
******* Description ***********
dcache_preload_size
******* Description ***********
dcache_prelock_ctrl
******* Description ***********
dcache_prelock_sct0_addr
******* Description ***********
dcache_prelock_sct1_addr
******* Description ***********
dcache_prelock_sct_size
******* Description ***********
dcache_sync_addr
******* Description ***********
dcache_sync_ctrl
******* Description ***********
dcache_sync_size
******* Description ***********
dcache_tag_power_ctrl
******* Description ***********
ibus_acs_cnt
******* Description ***********
ibus_acs_miss_cnt
******* Description ***********
ibus_to_flash_end_vaddr
******* Description ***********
ibus_to_flash_start_vaddr
******* Description ***********
icache_atomic_operate_ena
******* Description ***********
icache_autoload_ctrl
******* Description ***********
icache_autoload_sct0_addr
******* Description ***********
icache_autoload_sct0_size
******* Description ***********
icache_autoload_sct1_addr
******* Description ***********
icache_autoload_sct1_size
******* Description ***********
icache_ctrl
******* Description ***********
icache_ctrl1
******* Description ***********
icache_freeze
******* Description ***********
icache_lock_addr
******* Description ***********
icache_lock_ctrl
******* Description ***********
icache_lock_size
******* Description ***********
icache_preload_addr
******* Description ***********
icache_preload_ctrl
******* Description ***********
icache_preload_size
******* Description ***********
icache_prelock_ctrl
******* Description ***********
icache_prelock_sct0_addr
******* Description ***********
icache_prelock_sct1_addr
******* Description ***********
icache_prelock_sct_size
******* Description ***********
icache_sync_addr
******* Description ***********
icache_sync_ctrl
******* Description ***********
icache_sync_size
******* Description ***********
icache_tag_power_ctrl
******* Description ***********

Structs§

RegisterBlock
Register block

Type Aliases§

CACHE_ACS_CNT_CLR
CACHE_ACS_CNT_CLR (w) register accessor: ******* Description ***********
CACHE_BRIDGE_ARBITER_CTRL
CACHE_BRIDGE_ARBITER_CTRL (rw) register accessor: ******* Description ***********
CACHE_CONF_MISC
CACHE_CONF_MISC (rw) register accessor: ******* Description ***********
CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON
CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON (rw) register accessor: ******* Description ***********
CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE
CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE (rw) register accessor: ******* Description ***********
CACHE_ILG_INT_CLR
CACHE_ILG_INT_CLR (w) register accessor: ******* Description ***********
CACHE_ILG_INT_ENA
CACHE_ILG_INT_ENA (rw) register accessor: ******* Description ***********
CACHE_ILG_INT_ST
CACHE_ILG_INT_ST (r) register accessor: ******* Description ***********
CACHE_MMU_FAULT_CONTENT
CACHE_MMU_FAULT_CONTENT (r) register accessor: ******* Description ***********
CACHE_MMU_FAULT_VADDR
CACHE_MMU_FAULT_VADDR (r) register accessor: ******* Description ***********
CACHE_MMU_OWNER
CACHE_MMU_OWNER (rw) register accessor: ******* Description ***********
CACHE_MMU_POWER_CTRL
CACHE_MMU_POWER_CTRL (rw) register accessor: ******* Description ***********
CACHE_PRELOAD_INT_CTRL
CACHE_PRELOAD_INT_CTRL (rw) register accessor: ******* Description ***********
CACHE_REQUEST
CACHE_REQUEST (rw) register accessor: ******* Description ***********
CACHE_STATE
CACHE_STATE (r) register accessor: ******* Description ***********
CACHE_SYNC_INT_CTRL
CACHE_SYNC_INT_CTRL (rw) register accessor: ******* Description ***********
CACHE_TAG_CONTENT
CACHE_TAG_CONTENT (rw) register accessor: ******* Description ***********
CACHE_TAG_OBJECT_CTRL
CACHE_TAG_OBJECT_CTRL (rw) register accessor: ******* Description ***********
CACHE_TAG_WAY_OBJECT
CACHE_TAG_WAY_OBJECT (rw) register accessor: ******* Description ***********
CACHE_VADDR
CACHE_VADDR (rw) register accessor: ******* Description ***********
CACHE_WRAP_AROUND_CTRL
CACHE_WRAP_AROUND_CTRL (rw) register accessor: ******* Description ***********
CLOCK_GATE
CLOCK_GATE (rw) register accessor: ******* Description ***********
CORE0_ACS_CACHE_INT_CLR
CORE0_ACS_CACHE_INT_CLR (w) register accessor: ******* Description ***********
CORE0_ACS_CACHE_INT_ENA
CORE0_ACS_CACHE_INT_ENA (rw) register accessor: ******* Description ***********
CORE0_ACS_CACHE_INT_ST
CORE0_ACS_CACHE_INT_ST (r) register accessor: ******* Description ***********
CORE0_DBUS_REJECT_ST
CORE0_DBUS_REJECT_ST (r) register accessor: ******* Description ***********
CORE0_DBUS_REJECT_VADDR
CORE0_DBUS_REJECT_VADDR (r) register accessor: ******* Description ***********
CORE0_IBUS_REJECT_ST
CORE0_IBUS_REJECT_ST (r) register accessor: ******* Description ***********
CORE0_IBUS_REJECT_VADDR
CORE0_IBUS_REJECT_VADDR (r) register accessor: ******* Description ***********
CORE1_ACS_CACHE_INT_CLR
CORE1_ACS_CACHE_INT_CLR (w) register accessor: ******* Description ***********
CORE1_ACS_CACHE_INT_ENA
CORE1_ACS_CACHE_INT_ENA (rw) register accessor: ******* Description ***********
CORE1_ACS_CACHE_INT_ST
CORE1_ACS_CACHE_INT_ST (r) register accessor: ******* Description ***********
CORE1_DBUS_REJECT_ST
CORE1_DBUS_REJECT_ST (r) register accessor: ******* Description ***********
CORE1_DBUS_REJECT_VADDR
CORE1_DBUS_REJECT_VADDR (r) register accessor: ******* Description ***********
CORE1_IBUS_REJECT_ST
CORE1_IBUS_REJECT_ST (r) register accessor: ******* Description ***********
CORE1_IBUS_REJECT_VADDR
CORE1_IBUS_REJECT_VADDR (r) register accessor: ******* Description ***********
DATE
DATE (rw) register accessor: ******* Description ***********
DBUS_ACS_CNT
DBUS_ACS_CNT (r) register accessor: ******* Description ***********
DBUS_ACS_FLASH_MISS_CNT
DBUS_ACS_FLASH_MISS_CNT (r) register accessor: ******* Description ***********
DBUS_ACS_SPIRAM_MISS_CNT
DBUS_ACS_SPIRAM_MISS_CNT (r) register accessor: ******* Description ***********
DBUS_TO_FLASH_END_VADDR
DBUS_TO_FLASH_END_VADDR (rw) register accessor: ******* Description ***********
DBUS_TO_FLASH_START_VADDR
DBUS_TO_FLASH_START_VADDR (rw) register accessor: ******* Description ***********
DCACHE_ATOMIC_OPERATE_ENA
DCACHE_ATOMIC_OPERATE_ENA (rw) register accessor: ******* Description ***********
DCACHE_AUTOLOAD_CTRL
DCACHE_AUTOLOAD_CTRL (rw) register accessor: ******* Description ***********
DCACHE_AUTOLOAD_SCT0_ADDR
DCACHE_AUTOLOAD_SCT0_ADDR (rw) register accessor: ******* Description ***********
DCACHE_AUTOLOAD_SCT0_SIZE
DCACHE_AUTOLOAD_SCT0_SIZE (rw) register accessor: ******* Description ***********
DCACHE_AUTOLOAD_SCT1_ADDR
DCACHE_AUTOLOAD_SCT1_ADDR (rw) register accessor: ******* Description ***********
DCACHE_AUTOLOAD_SCT1_SIZE
DCACHE_AUTOLOAD_SCT1_SIZE (rw) register accessor: ******* Description ***********
DCACHE_CTRL
DCACHE_CTRL (rw) register accessor: ******* Description ***********
DCACHE_CTRL1
DCACHE_CTRL1 (rw) register accessor: ******* Description ***********
DCACHE_FREEZE
DCACHE_FREEZE (rw) register accessor: ******* Description ***********
DCACHE_LOCK_ADDR
DCACHE_LOCK_ADDR (rw) register accessor: ******* Description ***********
DCACHE_LOCK_CTRL
DCACHE_LOCK_CTRL (rw) register accessor: ******* Description ***********
DCACHE_LOCK_SIZE
DCACHE_LOCK_SIZE (rw) register accessor: ******* Description ***********
DCACHE_OCCUPY_ADDR
DCACHE_OCCUPY_ADDR (rw) register accessor: ******* Description ***********
DCACHE_OCCUPY_CTRL
DCACHE_OCCUPY_CTRL (rw) register accessor: ******* Description ***********
DCACHE_OCCUPY_SIZE
DCACHE_OCCUPY_SIZE (rw) register accessor: ******* Description ***********
DCACHE_PRELOAD_ADDR
DCACHE_PRELOAD_ADDR (rw) register accessor: ******* Description ***********
DCACHE_PRELOAD_CTRL
DCACHE_PRELOAD_CTRL (rw) register accessor: ******* Description ***********
DCACHE_PRELOAD_SIZE
DCACHE_PRELOAD_SIZE (rw) register accessor: ******* Description ***********
DCACHE_PRELOCK_CTRL
DCACHE_PRELOCK_CTRL (rw) register accessor: ******* Description ***********
DCACHE_PRELOCK_SCT0_ADDR
DCACHE_PRELOCK_SCT0_ADDR (rw) register accessor: ******* Description ***********
DCACHE_PRELOCK_SCT1_ADDR
DCACHE_PRELOCK_SCT1_ADDR (rw) register accessor: ******* Description ***********
DCACHE_PRELOCK_SCT_SIZE
DCACHE_PRELOCK_SCT_SIZE (rw) register accessor: ******* Description ***********
DCACHE_SYNC_ADDR
DCACHE_SYNC_ADDR (rw) register accessor: ******* Description ***********
DCACHE_SYNC_CTRL
DCACHE_SYNC_CTRL (rw) register accessor: ******* Description ***********
DCACHE_SYNC_SIZE
DCACHE_SYNC_SIZE (rw) register accessor: ******* Description ***********
DCACHE_TAG_POWER_CTRL
DCACHE_TAG_POWER_CTRL (rw) register accessor: ******* Description ***********
IBUS_ACS_CNT
IBUS_ACS_CNT (r) register accessor: ******* Description ***********
IBUS_ACS_MISS_CNT
IBUS_ACS_MISS_CNT (r) register accessor: ******* Description ***********
IBUS_TO_FLASH_END_VADDR
IBUS_TO_FLASH_END_VADDR (rw) register accessor: ******* Description ***********
IBUS_TO_FLASH_START_VADDR
IBUS_TO_FLASH_START_VADDR (rw) register accessor: ******* Description ***********
ICACHE_ATOMIC_OPERATE_ENA
ICACHE_ATOMIC_OPERATE_ENA (rw) register accessor: ******* Description ***********
ICACHE_AUTOLOAD_CTRL
ICACHE_AUTOLOAD_CTRL (rw) register accessor: ******* Description ***********
ICACHE_AUTOLOAD_SCT0_ADDR
ICACHE_AUTOLOAD_SCT0_ADDR (rw) register accessor: ******* Description ***********
ICACHE_AUTOLOAD_SCT0_SIZE
ICACHE_AUTOLOAD_SCT0_SIZE (rw) register accessor: ******* Description ***********
ICACHE_AUTOLOAD_SCT1_ADDR
ICACHE_AUTOLOAD_SCT1_ADDR (rw) register accessor: ******* Description ***********
ICACHE_AUTOLOAD_SCT1_SIZE
ICACHE_AUTOLOAD_SCT1_SIZE (rw) register accessor: ******* Description ***********
ICACHE_CTRL
ICACHE_CTRL (rw) register accessor: ******* Description ***********
ICACHE_CTRL1
ICACHE_CTRL1 (rw) register accessor: ******* Description ***********
ICACHE_FREEZE
ICACHE_FREEZE (rw) register accessor: ******* Description ***********
ICACHE_LOCK_ADDR
ICACHE_LOCK_ADDR (rw) register accessor: ******* Description ***********
ICACHE_LOCK_CTRL
ICACHE_LOCK_CTRL (rw) register accessor: ******* Description ***********
ICACHE_LOCK_SIZE
ICACHE_LOCK_SIZE (rw) register accessor: ******* Description ***********
ICACHE_PRELOAD_ADDR
ICACHE_PRELOAD_ADDR (rw) register accessor: ******* Description ***********
ICACHE_PRELOAD_CTRL
ICACHE_PRELOAD_CTRL (rw) register accessor: ******* Description ***********
ICACHE_PRELOAD_SIZE
ICACHE_PRELOAD_SIZE (rw) register accessor: ******* Description ***********
ICACHE_PRELOCK_CTRL
ICACHE_PRELOCK_CTRL (rw) register accessor: ******* Description ***********
ICACHE_PRELOCK_SCT0_ADDR
ICACHE_PRELOCK_SCT0_ADDR (rw) register accessor: ******* Description ***********
ICACHE_PRELOCK_SCT1_ADDR
ICACHE_PRELOCK_SCT1_ADDR (rw) register accessor: ******* Description ***********
ICACHE_PRELOCK_SCT_SIZE
ICACHE_PRELOCK_SCT_SIZE (rw) register accessor: ******* Description ***********
ICACHE_SYNC_ADDR
ICACHE_SYNC_ADDR (rw) register accessor: ******* Description ***********
ICACHE_SYNC_CTRL
ICACHE_SYNC_CTRL (rw) register accessor: ******* Description ***********
ICACHE_SYNC_SIZE
ICACHE_SYNC_SIZE (rw) register accessor: ******* Description ***********
ICACHE_TAG_POWER_CTRL
ICACHE_TAG_POWER_CTRL (rw) register accessor: ******* Description ***********