Type Alias W

pub type W = W<CACHE_FCTRL_SPEC>;

Register CACHE_FCTRL writer

Aliased Type

pub struct W { /* private fields */ }

Implementations

impl W

pub fn cache_req_en(&mut self) -> CACHE_REQ_EN_W<'_, CACHE_FCTRL_SPEC>

Bit 0 - Set this bit to enable Cache’s access and SPI0’s transfer.

pub fn cache_usr_cmd_4byte( &mut self, ) -> CACHE_USR_CMD_4BYTE_W<'_, CACHE_FCTRL_SPEC>

Bit 1 - Set this bit to enable SPI0 read flash with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31.

pub fn cache_flash_usr_cmd( &mut self, ) -> CACHE_FLASH_USR_CMD_W<'_, CACHE_FCTRL_SPEC>

Bit 2 - 1: The command value of SPI0 reads flash is SPI_MEM_USR_COMMAND_VALUE. 0: Hardware read command value, controlled by SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD, SPI_MEM_FREAD_DUAL and SPI_MEM_FASTRD_MODE bits.

pub fn fdin_dual(&mut self) -> FDIN_DUAL_W<'_, CACHE_FCTRL_SPEC>

Bit 3 - When SPI0 accesses to flash, set this bit to enable 2-bm in DIN phase.

pub fn fdout_dual(&mut self) -> FDOUT_DUAL_W<'_, CACHE_FCTRL_SPEC>

Bit 4 - When SPI0 accesses to flash, set this bit to enable 2-bm in DOUT phase.

pub fn faddr_dual(&mut self) -> FADDR_DUAL_W<'_, CACHE_FCTRL_SPEC>

Bit 5 - When SPI0 accesses to flash, set this bit to enable 2-bm in ADDR phase.

pub fn fdin_quad(&mut self) -> FDIN_QUAD_W<'_, CACHE_FCTRL_SPEC>

Bit 6 - When SPI0 accesses to flash, set this bit to enable 4-bm in DIN phase.

pub fn fdout_quad(&mut self) -> FDOUT_QUAD_W<'_, CACHE_FCTRL_SPEC>

Bit 7 - When SPI0 accesses to flash, set this bit to enable 4-bm in DOUT phase.

pub fn faddr_quad(&mut self) -> FADDR_QUAD_W<'_, CACHE_FCTRL_SPEC>

Bit 8 - When SPI0 accesses to flash, set this bit to enable 4-bm in ADDR phase.